Github_Repos/cvw
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5,053 Commits 5 Branches 2 Tags 53 MiB
0d7653f1c7
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2039 Commits

Author SHA1 Message Date
Ross Thompson
0d7653f1c7 Removed the old two port ram and replaced it with the fixed version. 
The fixed version is renamed to ram2p1r1wb.sv
 2023-01-24 17:25:16 -06:00
Ross Thompson
3d07f7a3a2 Moved and ranamed btb to btb.sv 
Fixed btb to use the fixed port 2 sram.
 2023-01-24 17:19:51 -06:00
Ross Thompson
7ae6b1868e Partial BTB cleanup. 2023-01-24 16:12:35 -06:00
Ross Thompson
879cb77b90 Moved branch predictor files into separate sub-directory. 2023-01-24 16:00:27 -06:00
Ross Thompson
89698a929e Moved ebufsmarb into its own module. 2023-01-23 23:10:10 -06:00
Ross Thompson
d495d7b04d Added comments about needing move ebufsm into a new module. 2023-01-23 22:03:49 -06:00
Ross Thompson
45094fc7bb Added comments to lrsc module. 2023-01-23 17:49:47 -06:00
Ross Thompson
e1c121fe0d Oups fixed bug from the last commit. 2023-01-23 17:38:30 -06:00
Ross Thompson
bb11de0f4c Another round of cleanup in the LSU. 2023-01-23 17:27:39 -06:00
David Harris
678a879415 formatting 2023-01-23 10:54:06 -08:00
David Harris
b6b67516eb Repo cleanup 2023-01-23 10:37:33 -08:00
Ross Thompson
07308e2c14 Removed mark_debug from all source code. 2023-01-20 18:47:36 -06:00
David Harris
c2f7f7324d test 2023-01-20 15:23:38 -08:00
David Harris
b173112f86 Continued framework for B instructions 2023-01-20 14:27:13 -08:00
David Harris
1933ea39fa Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-20 14:19:10 -08:00
David Harris
0f68fccf82 Started adding bit manipulation unit 2023-01-20 14:19:07 -08:00
Ross Thompson
3d71d0196c Updated figure cache references. 2023-01-20 15:01:54 -06:00
Ross Thompson
5b740fbf60 Removed SDC from repo due to copy right issue. 
Modified fpga build flow to reference it outside the repo.
 2023-01-20 14:57:06 -06:00
Ross Thompson
b1f3bd566c Formatting. 2023-01-20 13:13:05 -06:00
Ross Thompson
f78bfc4940 Formatting. 2023-01-20 13:09:42 -06:00
Ross Thompson
c7f4970597 Formatting. 2023-01-20 13:05:10 -06:00
Ross Thompson
6142c96946 Reformatting cachefsm. 2023-01-20 12:49:55 -06:00
Ross Thompson
7e96f3e8f7 Formatting. 2023-01-20 12:41:57 -06:00
Ross Thompson
95de716a17 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-20 12:37:12 -06:00
Ross Thompson
b8a699270e More cleanup and formatting. 2023-01-20 12:34:40 -06:00
David Harris
032332ebae renamed comparator module 2023-01-20 10:13:47 -08:00
Ross Thompson
f1049be6c1 More cleanup and formatting. 2023-01-20 12:09:21 -06:00
Ross Thompson
4a2d02ab28 Formatting. 2023-01-20 11:51:10 -06:00
Ross Thompson
11c44006c4 Integrated the missing zifence tests into the regression test. 2023-01-20 10:34:49 -06:00
Ross Thompson
eb19b1b499 Imperas found a bug with the Fence.I instruction. 
If a fence.i directly followed a store miss, the d$ would release Stall during the cache line write.
Then transition to ReadHold.  This cause the d$ flush to go high while in ReadHold.  The solution is
to ensure the cache continues to assert Stall while in WriteLine state.

There was a second issue also.  The D$ flush asserted FlushD which flushed the I$ invalidate.
Finally the third issue was CacheEn from the FSM needs to be asserted on an InvalidateCache.
 2023-01-20 10:17:21 -06:00
Ross Thompson
63dbebcb5a Improved comment. 2023-01-19 17:41:57 -06:00
Ross Thompson
91bd55d9ba ram uses always rather than always_ff due to modelsim issue. 2023-01-19 17:41:15 -06:00
Ross Thompson
30935fd2b7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-19 17:28:53 -06:00
Ross Thompson
78e8598ec8 Added comment about needed changes in BTB. 2023-01-19 17:28:00 -06:00
David Harris
aed6f79d1e Removed study versions from comparator 2023-01-19 15:13:35 -08:00
David Harris
ad3b528b5d Moved unused study files to studies directory 2023-01-19 15:13:11 -08:00
David Harris
264362ce17 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-19 14:47:54 -08:00
David Harris
a1b25e1039 RAM declaration cleanup: 2023-01-19 14:47:51 -08:00
Ross Thompson
75391f4b56 Formatting. 2023-01-19 15:06:37 -06:00
Ross Thompson
40d62ec0d1 Formatting. 2023-01-19 14:18:46 -06:00
Ross Thompson
999477bb02 Formatting and name changes. 2023-01-19 14:16:29 -06:00
Ross Thompson
0bbf6e4ae2 Formatting. 2023-01-18 19:26:20 -06:00
Ross Thompson
21b2b10e78 Formatting spillsupport. 2023-01-18 19:25:54 -06:00
Ross Thompson
db48e547f0 Formatting. 2023-01-18 19:11:30 -06:00
Ross Thompson
9170827c98 Reduced complexity of spill logic by ensuring the irom outputs offset instrutions on a spill. 2023-01-18 19:10:34 -06:00
Ross Thompson
e79c403fe1 More IROM cleanup. 2023-01-18 18:47:02 -06:00
Ross Thompson
63577cbf4a Cleanup dtim and irom. 2023-01-18 18:44:30 -06:00
Ross Thompson
2d945963e6 Added comments to decompress.sv. May want to consider additional documentation. 2023-01-18 18:26:51 -06:00
Ross Thompson
f34c67722d Formatted subword* and bytemask. 2023-01-18 18:20:22 -06:00
Ross Thompson
f288b9ca14 Formatting. 2023-01-18 18:17:48 -06:00