Ross Thompson
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6734685333
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Fixed connection bugs in the top level fpga which preventing sending ethernet frames back to the trigger in unit.
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2024-07-09 19:04:18 -05:00 |
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Ross Thompson
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ccf4bb8ddc
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Maybe have the incircuit trigger working.
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2024-06-26 16:15:46 -07:00 |
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Ross Thompson
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612a281f62
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Added module to receive ethernet frame and trigger the ila.
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2024-06-26 11:05:31 -07:00 |
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Ross Thompson
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1c6ebb86a3
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Added some debug code to count frames sent to the ethernet mac and frames sent to the phy.
Removed the external reset of the phy and now it always reliably starts in the same way. The first 0x117 frames are always captured.
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2024-06-20 12:54:12 -07:00 |
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Ross Thompson
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47523c97ac
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Getting closer to figuring out the lost ethernet frame bugs.
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2024-06-13 15:46:54 -07:00 |
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Ross Thompson
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c9f51df34a
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Fixed bug in rvvi reset.
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2024-06-12 14:47:32 -07:00 |
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Rose Thompson
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6a4c8667df
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Added new signals to ILA to debug the RVVI tracer.
The tracer appears to be stuck and the CPU is never getting out of (into reset).
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2024-05-30 16:43:25 -05:00 |
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Rose Thompson
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9703055758
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The FPGA is synthesizing with the rvvi and ethernet hardware.
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2024-05-30 15:37:17 -05:00 |
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Rose Thompson
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7693c5d4e2
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Updates to fpga top level.
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2023-12-15 15:32:05 -06:00 |
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Rose Thompson
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26cd22c388
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Replaced fpga's verilog top with system verilog.
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2023-12-15 13:42:52 -06:00 |
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Rose Thompson
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dab9d7ab3c
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Replaced fpga top level verilog with system verilog.
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2023-12-15 13:07:08 -06:00 |
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