Kevin Thomas
1931859c45
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-04-06 12:38:41 -05:00
David Harris
fddbd79209
Update dvtestplan.md
2023-04-06 09:29:47 -07:00
David Harris
6431e358ca
Create dvtestplan.md
2023-04-06 09:23:09 -07:00
David Harris
4448c238c4
Merge pull request #214 from eroom1966/main
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Add in configuration for B extension
2023-04-06 09:08:20 -07:00
Lee Moore
a20528e43c
Merge branch 'openhwgroup:main' into main
2023-04-06 16:31:49 +01:00
eroom1966
430763a1d1
add support into configuration for Zb(a,b,c,s)
2023-04-06 16:30:14 +01:00
David Harris
2a3711546f
Merge pull request #213 from eroom1966/main
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fix break to simulation testbench
2023-04-06 06:54:59 -07:00
eroom1966
319a1b9161
fix break to simulation testbench
2023-04-06 14:45:41 +01:00
David Harris
52dcd63d1e
Merge pull request #211 from ross144/main
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Fixes the issue introduced by the fix for issue 203
2023-04-05 21:50:32 -07:00
Ross Thompson
1478115faf
Fixed wally64/32priv test hangup.
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The fix for the issue 203 had a lingering bug which did not suppress a bus access if the hptw short circuits on a pma/p fault.
2023-04-05 23:13:45 -05:00
Kevin Thomas
5d71960385
Merge branch 'main' of https://github.com/kjprime/cvw
2023-04-05 17:44:54 -05:00
Kevin Thomas
0b317c4823
Merge branch 'openhwgroup:main' into main
2023-04-05 17:44:47 -05:00
Kevin Thomas
e70a081924
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-04-05 17:43:43 -05:00
Ross Thompson
f2c26ff886
Merge pull request #206 from AlecVercruysse/coverage2
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i$ coverage improvements
2023-04-05 17:29:35 -05:00
David Harris
b3cf1b45fa
Merge pull request #210 from SydRiley/main
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Starting to extend fpu conditional coverage, reformatting ifu test cases.
2023-04-05 14:56:16 -07:00
Alec Vercruysse
2a3d9f8c89
Update ram1p1rwe (ce & we) coverage exlusion explanation
2023-04-05 14:54:58 -07:00
Sydeny
d264d3274c
Starting to extend fpu conditional coverage, reformating ifu test cases
2023-04-05 14:10:15 -07:00
Kevin Thomas
29dec429a0
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-04-05 15:33:10 -05:00
Kevin Thomas
c4a9bb4269
Formating white space
2023-04-05 15:30:55 -05:00
David Harris
7963bfdbe5
Merge pull request #205 from kbox13/my-single-change
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Increase LSU Coverage
2023-04-05 13:16:04 -07:00
Kevin Thomas
7345927cb1
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-04-05 15:04:12 -05:00
David Harris
af58afd054
Merge pull request #208 from ross144/main
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Fixes Issue 203
2023-04-05 13:03:30 -07:00
Ross Thompson
90c2156164
Merge pull request #207 from AlecVercruysse/cachesim
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Cache Simulator
2023-04-05 14:59:52 -05:00
Ross Thompson
d1ac175e27
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-04-05 14:55:12 -05:00
Limnanthes Serafini
5bae4801bb
*.out removal
2023-04-05 12:50:26 -07:00
Limnanthes Serafini
69eecac989
*.out removal
2023-04-05 12:50:10 -07:00
Limnanthes Serafini
6f53531e26
*.out removal
2023-04-05 12:49:57 -07:00
Alec Vercruysse
61e19c2ddf
Make CacheWay flush and dirty logic dependent on !READ_ONLY_CACHE
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To increase coverage. Read-only caches do not have flushes since
they do not have dirty bits.
2023-04-05 11:48:18 -07:00
Alec Vercruysse
d3a988c96c
make Cache Flush Logic dependent on !READ_ONLY_CACHE
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read-only caches do not have flush logic since they do not have to
deal with dirty bits.
2023-04-05 11:48:18 -07:00
Alec Vercruysse
247af17b6b
remove ClearValid from cache
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The cachefsm hardwired ClearValid logic to zero.
This signal might've been added to potentially add extra functionality
later. Unless that functionality is added, however, it negatively
impacts coverage. If the goal is to maximize coverage, this signal
should be removed and only added when it becomes necessary.
2023-04-05 11:48:18 -07:00
Alec Vercruysse
3867142f10
change i$ cachetagmem from ram1p1rwbe -> ram1p1rwe
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the byte write-enables were always tied high, so we can use
RAM without byte-enable to increase coverage.
2023-04-05 11:48:18 -07:00
Alec Vercruysse
4993b1b426
turn off ce coverage for ram1p1rwe
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According to the textbook, the cache memory chip enable,
`CacheEn`, is only lowered by the cachefsm with it is in the ready
state and a pipeline stall is asserted.
For read only caches, cache writes only occur in the state_write_line
state. So there is no way that a write would happen while the chip
enable is low.
Removing the chip-enable check from this memory to increase coverage
would be a bad idea since if anyone else uses this ram, the behaviour
would be differently than expected. Instead, I opted to turn off
coverage for this statement. Since this ram, which does not have a
byte enable, is used exclusively by read-only caches right now, this
should not mistakenly exclude coverage for other cases, such as D$.
2023-04-05 11:48:18 -07:00
Alec Vercruysse
277f507e9a
add ram1p1rwe for read-only cache ways (remove byte-enable)
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- increases coverage
2023-04-05 11:48:18 -07:00
Alec Vercruysse
c0206cfcb3
fix typo in cachway setValid input comment
2023-04-05 11:48:18 -07:00
Alec Vercruysse
270200bc1c
put cacheLRU coverage explanation on another line
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the `: explanation` syntax was not working
2023-04-05 11:48:18 -07:00
Alec Vercruysse
c41f4d2e7b
Exclude CacheLRU log2 function from coverage
2023-04-05 11:48:18 -07:00
Ross Thompson
7c2512446c
Progress on bug 203.
2023-04-05 13:20:04 -05:00
Kevin Box
c43ee180d3
Add sfence.vma
2023-04-05 10:34:30 -07:00
Kevin Box
490cebe36b
Revert "Add sfence.vma and arch64d/f tests to increase coverage in the LSU"
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This reverts commit 90b5d279fd
2023-04-05 10:32:25 -07:00
Kevin Box
0517c6b2be
remove testing changes
2023-04-05 10:27:34 -07:00
Kevin Box
2c1a0c19dc
remove testing change
2023-04-05 10:27:11 -07:00
Kevin Box
90b5d279fd
Add sfence.vma and arch64d/f tests to increase coverage in the LSU
2023-04-05 10:18:41 -07:00
Limnanthes Serafini
7de772dcfe
Merge remote-tracking branch 'upstream/main' into cachesim
2023-04-05 09:53:05 -07:00
Kevin Thomas
5e5842893b
Minor change with the IFU in the decompress module, in the compressed instruction truth table.
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The truth table is already fully covered, removed redundant last case checking
2023-04-05 10:27:52 -05:00
David Harris
7373cbb3ff
Merge pull request #201 from ross144/main
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Improved d/i cache loggers
2023-04-05 06:40:14 -07:00
Limnanthes Serafini
98a56dcd66
Further comments and attribution.
2023-04-05 02:46:31 -07:00
Limnanthes Serafini
c42d798ff4
Commenting, attribution for sim, minor log changes
2023-04-05 02:43:02 -07:00
Limnanthes Serafini
47a8cf3993
Outfiles for the failing tests.
2023-04-05 02:42:09 -07:00
Limnanthes Serafini
6abd4ee1b7
Changed logging enables, debug mode in sim.
2023-04-04 23:49:35 -07:00
Limnanthes Serafini
8f3413f0d5
CacheSim edits, tests. I/D$ logging, Lim's version
2023-04-04 21:12:35 -07:00
