David Harris
8bf9329815
Added M suffix in atomic
2023-04-24 12:19:56 -07:00
David Harris
1278e231ff
Merge pull request #275 from dherreravicioso/main
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Excluded coverage for impossible cases in wficountreg and status.MPRV
2023-04-24 12:18:55 -07:00
Ross Thompson
89a242d143
Might actually have a correct implementation of local history branch prediction.
2023-04-24 13:05:28 -05:00
Ross Thompson
7588de5a36
Fixed the local branch predictor so that it at least compiles.
2023-04-24 11:06:53 -05:00
Diego Herrera Vicioso
c681789296
Excluded coverage for impossible cases in wficountreg and status.MPRV
2023-04-24 02:06:53 -07:00
Ross Thompson
994a43a3fa
Merge pull request #272 from davidharrishmc/dev
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fdivsqrt coverage and fix bug of not trapping on access to odd-numbered pmpcfg
2023-04-23 12:22:14 -05:00
David Harris
1d532dfcfc
Fault on writes to odd-numbered PMPCFG in RV64
2023-04-22 15:32:39 -07:00
David Harris
a5b80bc440
Removed unproven fdivsqrt exclusion
2023-04-22 15:27:05 -07:00
David Harris
8be5ed9b67
Attempted to cause interrupt during fdivsqrt. Fixed enabling fpu in fpu.S. Fdivsqrt exclusions for coverage.
2023-04-22 12:22:45 -07:00
David Harris
0871bbe8f2
Fixted syntax error in exclusion. Arbitrarily picked -e 1; fix if this isn't right
2023-04-22 10:07:48 -07:00
David Harris
87aff3dcc7
test plan update
2023-04-22 09:38:14 -07:00
David Harris
0c459e5edd
Merge pull request #270 from liamchalk00/main
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pmpcfg test cases
2023-04-22 08:41:11 -07:00
Liam
2ed9384238
pmpcfg test cases
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Increased IFU coverage from 83.37% to 83.53% and LSU coverage from 93.14% to 93.28%.
2023-04-21 20:43:37 -07:00
Ross Thompson
884c3c22d5
Merge pull request #266 from davidharrishmc/dev
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FDivSqrt cleanup
2023-04-21 20:23:23 -05:00
Ross Thompson
f872be6fc3
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-04-21 12:46:22 -05:00
Ross Thompson
d513956bb9
Updated fpga Makefile to work with both the Arty and VCU platforms.
2023-04-21 11:08:35 -05:00
David Harris
e11212598f
fdivsqrt cleanup
2023-04-20 17:35:01 -07:00
David Harris
f9ca280e01
continued cleanup
2023-04-20 16:48:23 -07:00
David Harris
ea7c50e0ee
Reordered fdivsqrtpreproc to follow logic
2023-04-20 16:38:47 -07:00
David Harris
ca0269c094
Started fdivsqrtpreproc flow organization
2023-04-20 16:25:19 -07:00
David Harris
c431278fe6
Fmv h/q comments in controller
2023-04-20 16:24:58 -07:00
David Harris
b8c2062698
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-04-20 16:07:37 -07:00
David Harris
94d1533264
Merge pull request #256 from cturek/main
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Simplifying fds to follow diagram
2023-04-20 16:07:22 -07:00
David Harris
0fddad2fd4
Merge pull request #265 from Noah-G-L/main
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Add Coverage for TLB, MP, Global, ASID and Match
2023-04-20 16:06:09 -07:00
Noah Limpert
cf150a2ea9
Add in a test that makes match 3 = 0 for all tlb lines
2023-04-20 14:50:06 -07:00
Noah Limpert
73cca666bf
Commiting changes to add coverage to ASID, Global, Megapage size checks.
2023-04-20 14:38:13 -07:00
David Harris
870c15c4f5
Update README.md
2023-04-20 14:15:34 -07:00
David Harris
5f14dfe748
Update README.md
2023-04-20 14:09:32 -07:00
Ross Thompson
ffa686a605
Merge pull request #264 from davidharrishmc/dev
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Added -fp flag to run arch64d/f tests in coverage
2023-04-20 09:26:16 -05:00
David Harris
9fac2b6e57
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-04-19 14:50:09 -07:00
David Harris
24e60c232d
Merge pull request #262 from SydRiley/main
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removed comments for fixed bugs in fpu, increased coverage in fpu, ifu, and lsu: fpu from 93.51% to 93.62%, ifu from 78.56% to 78.75%, lsu from 88.96% to 88.98%
2023-04-19 14:49:50 -07:00
Sydeny
039a06ec95
clarifying comments in exclusions
2023-04-19 14:47:34 -07:00
Sydeny
b76ed145e6
removed comments for fixed bugs in fpu, increased coverage: fpu from 93.51% to 93.62%, ifu from 78.56% to 78.75%, lsu from 88.96% to 88.98%
2023-04-19 13:30:12 -07:00
David Harris
a3f3967f59
Added -fp flag to run arch64d/f tests in coverage
2023-04-19 13:07:07 -07:00
David Harris
a4cc3c6b3e
Merge pull request #261 from liamchalk00/main
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Add pmpcfg test cases increasing IFU coverage
2023-04-19 12:37:19 -07:00
Liam
2684a81754
Add pmpcfg test cases increasing IFU coverage
2023-04-19 11:58:22 -07:00
Ross Thompson
a6903ac5f3
Yeah We boot linux on the arty a7!
2023-04-19 11:17:33 -05:00
Ross Thompson
c463bd8cdd
Fixed the reset for Arty A7 and now partially boots. Copies flash card to dram.
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but the data is wrong.
2023-04-19 10:35:18 -05:00
David Harris
68295bd750
Update tests.vh
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Missing comma from merge
2023-04-19 06:23:05 -07:00
David Harris
5ac756b685
Merge pull request #259 from AlecVercruysse/coverage4
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D$ Coverage
2023-04-19 06:17:01 -07:00
David Harris
79dbfae4af
Merge branch 'main' into coverage4
2023-04-19 06:16:07 -07:00
David Harris
c36d3cb32b
Merge pull request #258 from liamchalk00/main
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Add test cases for pmpcfg.S
2023-04-19 04:52:59 -07:00
David Harris
59d153ace0
Merge branch 'main' into main
2023-04-19 04:50:12 -07:00
David Harris
2beb32e6b9
Merge pull request #257 from koooo142857/main
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PMPCFG_ARRAY_REGW cases
2023-04-19 04:47:12 -07:00
David Harris
a13feb5d0b
Merge branch 'main' into main
2023-04-19 04:46:51 -07:00
David Harris
f4a949c28c
Merge pull request #255 from kjprime/main
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Add PR#252 test file to coverage
2023-04-19 04:43:25 -07:00
Alec Vercruysse
7ba2bfd4b6
CacheFSM logic simplification for AMO operations
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Ran this by Ross.
2023-04-19 01:34:01 -07:00
Alec Vercruysse
b52512b1ae
D$ scope-specific coverage exclusions (I$ logic that never fires)
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The InvalidateCache signal in the D$ is for I$ only, which
causes some coverage issues that need exclusion.
Another manual exclusion is due to the fact that D$ writeback, flush,
write_line, or flush_writeback states can't be cancelled by a flush,
so those transistions are excluded.
There is some other small stuff to review (logic simplification,
or an exclusion pragma if removing the redundent logic would
make it harder to understand the code, as is the case in the
FlushAdrCntEn assign statement, in my opinion).
2023-04-19 01:34:01 -07:00
Alec Vercruysse
3de03abd9d
add D$ test case to trigger a FlushStage while SetDirtyWay=1
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This hits some conditional coverage in each cacheway.
A cache store hit happens at the same time as a StoreAmoMisalignedFault.
2023-04-19 01:34:01 -07:00
Alec Vercruysse
cd9feb0260
Cover CacheWay edge case: CacheDataMem we=1 while ce=0.
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This test basically triggers an i$ miss during a d$ (hit) store
operation. It requires some tricky timing (e.g. a flushD right
before the relevant store). I use a script to generate the test.
2023-04-19 01:34:01 -07:00
