Ross Thompson
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f9ffcf377b
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Reverted the IROM/DTIM address range modelsim assignment.
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2022-11-30 17:13:33 -06:00 |
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David Harris
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76006825b3
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Set bit width of DMEM/IROM_SUPPORTED and fixed address decoding
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2022-08-26 21:18:18 -07:00 |
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David Harris
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6409548c8b
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Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each
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2022-08-26 20:26:12 -07:00 |
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David Harris
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906f6f2990
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Renamed DMEM to DTIM and added checks about compatibility of DTIM/IROM and virtmem
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2022-08-26 20:12:03 -07:00 |
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Ross Thompson
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bd9401179d
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BROKEN. Don't use this commit.
Issue running cacheless with bus.
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2022-08-25 11:02:46 -05:00 |
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Ross Thompson
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b650d7e05a
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Renamed RAM to UNCORE_RAM.
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2022-08-24 18:09:07 -05:00 |
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Ross Thompson
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c6927d2ace
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Modified the lsu/ifu memory configurations.
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2022-08-24 12:35:15 -05:00 |
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Ross Thompson
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856ac24686
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Removed replay from the config files.
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2022-07-24 00:34:11 -05:00 |
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slmnemo
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7c019ea074
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Removed references to initialization files
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2022-06-23 16:50:27 -07:00 |
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DTowersM
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dd34f25ffd
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changed DCACHE_LINELENINBITS and ICACHE_LINELENINBITS to 512, had to modigy the wfi test to increase timee before interupt to mantain compatability
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2022-06-10 00:37:53 +00:00 |
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slmnemo
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65961223f8
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Updated Linux testbench to use new force/unforce method for Branch predictor init and removed related .txt files
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2022-06-02 02:51:51 +00:00 |
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David Harris
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4f1b0fdc64
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Preliminary support for big endian modes. Regression passes but no big endian tests written yet.
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2022-05-08 06:46:35 +00:00 |
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Kip Macsai-Goren
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746fcfde30
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set WFI timeout to after 16 bits of counting for all configs
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2022-04-28 18:14:08 +00:00 |
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Shreya Sanghai
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a8b3cc8cf9
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added bpred size to wally config
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2022-04-18 04:21:03 +00:00 |
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David Harris
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b4902a6ff9
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First implementation of WFI timeout wait
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2022-04-17 17:20:35 +00:00 |
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Katherine Parry
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c3d07b2c46
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generating all testfloat vectors
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2022-04-04 17:17:12 +00:00 |
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Ross Thompson
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67ff8f27f4
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Can now support the following memory and bus configurations.
1. dtim/irom only
2. bus only
3. dtim/irom + bus
4. caches + bus
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2022-03-11 15:18:56 -06:00 |
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bbracker
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202bd2f8f8
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change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests
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2022-02-22 03:46:08 +00:00 |
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Ross Thompson
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0bd533473c
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New config option to enable hptw writes to PTE in memory to update Access and Dirty bits.
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2022-02-17 17:19:41 -06:00 |
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Ross Thompson
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4273775a2b
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-02-08 14:22:19 -06:00 |
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David Harris
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510b47523a
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rv32e config update
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2022-02-08 17:59:50 +00:00 |
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Ross Thompson
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853a7bba18
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-02-08 11:36:30 -06:00 |
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Ross Thompson
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8a2ee22395
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Finished merge.
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2022-02-08 11:36:24 -06:00 |
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David Harris
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64e9f4c0d3
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Restored E tests to makefrag
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2022-02-08 16:41:11 +00:00 |
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David Harris
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c61cd55c5c
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Merged TIM and regular testbenches. RV32e now working and back in regression.
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2022-02-08 12:18:13 +00:00 |
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David Harris
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0f7b8017d1
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Modified regression to use proper rv32e test name, but rv32e_wally32e still isn't passing due to loop exceeding iteration limit
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2022-02-05 05:35:51 +00:00 |
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David Harris
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72bc64ef28
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Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests.
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2022-02-05 04:16:18 +00:00 |
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David Harris
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fb041fe06a
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rv32e
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2022-02-04 01:56:30 +00:00 |
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David Harris
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4ba37d5cc0
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Config file & wally-riscv-arch-test cleanup
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2022-02-02 16:35:52 +00:00 |
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David Harris
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748375c82f
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Updated configs to fix GPIO address to match FU540
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2022-01-26 18:16:34 +00:00 |
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David Harris
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b63e53bbdb
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Defined rv32e and rv32emc configs
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2022-01-17 14:01:01 +00:00 |
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