Commit Graph

17 Commits

Author SHA1 Message Date
Alec Vercruysse
5612f30029 Cacheway Exclude FlushStage=1 when SetValidWay=1
We determined that this case is not hit even for i$, so this
case is also excluded separately for i$. It could be a better
idea to remove the ~FlushStage check completely (if we're sure).

My reasoning for this one is written as a comment in the exclusion
script: since a pipeline stall is asserted by the cache in the fetch
stage (which happens before going into the WRITE_LINE state and
asserting SetValidWay), there seems to be no way to trigger
a FlushStage (FlushW for D$) while the stallM is active.
2023-04-25 20:30:46 -07:00
Alec Vercruysse
857956ac1e Cacheway exclude SelFlush=0 while FlushWay=0 in FlushWayEn assign
FlushWay is always 1 for one way, but by default it is only 1 for
way 0.

The logic that advances FlushWay to ways 1, 2, and 3 only does so
on a subset of conditions that SelFlush is high (in cachefsm), so
this is unreachable for cachways 1-3.
2023-04-25 17:02:53 -07:00
Alec Vercruysse
de93bd6937 D$ scope-specific coverage exclusions (I$ logic that never fires)
The InvalidateCache signal in the D$ is for I$ only, which
causes some coverage issues that need exclusion.

Another manual exclusion is due to the fact that D$ writeback, flush,
write_line, or flush_writeback states can't be cancelled by a flush,
so those transistions are excluded.

There is some other small stuff to review (logic simplification,
or an exclusion pragma if removing the redundent logic would
make it harder to understand the code, as is the case in the
FlushAdrCntEn assign statement, in my opinion).
2023-04-19 01:34:01 -07:00
Ross Thompson
30e3d2cdce Merge pull request #233 from AlecVercruysse/coverage3
Full I$ coverage
2023-04-14 22:15:11 -05:00
Alec Vercruysse
4d9aa72877 replace instances of code duplication for i$ exclusions w/commands 2023-04-14 17:10:39 -07:00
Limnanthes Serafini
034c289a36 Misc typo and indent fixing. 2023-04-13 16:54:15 -07:00
Alec Vercruysse
0ed3e80ee0 only assign ClearDirtyWay for read-write caches 2023-04-12 01:15:35 -07:00
Alec Vercruysse
68a01cb0f8 Exclude (FlushStage & SetValidWay) condition for RO caches
Spent a long time trying to find a way to see if this condition was
possible, only to become relativly convinced that it isn't.
Basically, since RO cache writes only happen after a long period of
stall for the bus access, there's no way a flushD can be active
at the same time as a RO cache write. TrapM causes a FlushD, but
interrupts are gated by the "commited" logic and the exception
pipeline stalls.

I feel like its worth keeping the logic to be safe
so I've chosen to exclude it rather than explicitely remove it.
2023-04-12 01:15:35 -07:00
Alec Vercruysse
570e86afc3 Make CacheWay flush and dirty logic dependent on !READ_ONLY_CACHE
To increase coverage. Read-only caches do not have flushes since
they do not have dirty bits.
2023-04-05 11:48:18 -07:00
Alec Vercruysse
3419ef3651 remove ClearValid from cache
The cachefsm hardwired ClearValid logic to zero.
This signal might've been added to potentially add extra functionality
later. Unless that functionality is added, however, it negatively
impacts coverage. If the goal is to maximize coverage, this signal
should be removed and only added when it becomes necessary.
2023-04-05 11:48:18 -07:00
Alec Vercruysse
81125d3180 change i$ cachetagmem from ram1p1rwbe -> ram1p1rwe
the byte write-enables were always tied high, so we can use
RAM without byte-enable to increase coverage.
2023-04-05 11:48:18 -07:00
Alec Vercruysse
8b6b96012d add ram1p1rwe for read-only cache ways (remove byte-enable)
- increases coverage
2023-04-05 11:48:18 -07:00
Alec Vercruysse
2553321158 fix typo in cachway setValid input comment 2023-04-05 11:48:18 -07:00
Ross Thompson
b5a58502d0 Replaced tabs -> spaces cache. 2023-03-24 15:15:38 -05:00
Ross Thompson
c190444fa2 Updated CAdr to CacheSet. 2023-03-13 14:53:00 -05:00
Ross Thompson
a5523400ae Replaced DCACHE parameter with READ_ONLY_CACHE as the name was confusing in chapter 10. 2023-03-12 13:21:22 -05:00
David Harris
78eb90715c Removed pipelined level of hierarchy 2023-02-02 14:14:11 -08:00