77 Commits

Author	SHA1	Message	Date
James E. Stine	12e09a7ace	slight mod to fpdiv - still bug in batch vs. non-batch	2021-07-20 01:47:46 -04:00
David Harris	2ed6285a3d	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-19 10:34:18 -04:00
James Stine	7d571f27a6	delete sbtm_a4 and sbtm_a5 as they are not needed	2021-07-19 08:06:00 -05:00
James Stine	186b5dee69	remove sbtm3.sv - not needed	2021-07-19 08:00:53 -05:00
James Stine	5b1f9797f5	update part I on sbtm change	2021-07-19 07:59:27 -05:00
David Harris	8e01007d1c	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-19 00:25:06 -04:00
Katherine Parry	c9180f4ebd	FDIV and FSQRT passes when simulating in modelsim	2021-07-18 23:00:04 -04:00
David Harris	46ab609498	Updated FMA1 with parameterized size	2021-07-18 20:40:49 -04:00
David Harris	ed64d37e65	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-18 17:36:29 -04:00
David Harris	4f8f52f283	Added FLEN, NE, NF to config and started using these in FMA1	2021-07-18 17:28:25 -04:00
Katherine Parry	60dabb9094	fdivsqrt inegrated, but not completley working	2021-07-18 14:03:37 -04:00
Katherine Parry	c74d26eea4	Fixed lint warning	2021-07-14 21:24:48 -04:00
Katherine Parry	f5bfdf46db	fpu unpacking unit created	2021-07-14 17:56:49 -04:00
James Stine	e6d19be87c	put back for now to test fdiv	2021-07-14 06:48:29 -05:00
James E. Stine	46001fef27	mod 2 of fpdivsqrt update	2021-07-13 16:59:17 -04:00
James E. Stine	8382a17969	Update fpdivsqrt item until move into uarch	2021-07-13 16:53:20 -04:00
Katherine Parry	efdec72df1	Fixed writting MStatus FS bits	2021-07-13 13:20:30 -04:00
Katherine Parry	f3ac46df86	fcvt.sv cleanup	2021-07-11 21:30:01 -04:00
Katherine Parry	36f59f3c99	Almost all convert instructions pass Imperas tests	2021-07-11 18:06:33 -04:00
David Harris	5f91b339aa	Added F_SUPPORTED flag to disable floating point unit when not in MISA	2021-07-05 10:30:46 -04:00
David Harris	ac163e091c	Fixed disabling MulDiv when not supported. Started adding generate for FPU unsupported	2021-07-04 19:33:46 -04:00
David Harris	accbebfa6f	Commented out some unused modules	2021-07-04 01:40:27 -04:00
Katherine Parry	308c9ccaac	FPU update - missing files	2021-07-02 12:53:05 -04:00
Katherine Parry	30ff212ca8	FPU update	2021-07-02 12:40:58 -04:00
Katherine Parry	0c2b7a1132	FPU control signals changed and FMA works	2021-06-28 18:53:58 -04:00
Katherine Parry	7e3483b283	FPU forwarding reworked pt.1	2021-06-24 18:39:18 -04:00
Katherine Parry	8eed89616c	fpu clean-up	2021-06-23 16:42:40 -04:00
Katherine Parry	353a27f12f	rv64f FLW passes imperas tests	2021-06-22 16:36:16 -04:00
Katherine Parry	2b67f25683	all rv64f instructions except convert, divide, square root, and FLD pass	2021-06-20 20:24:09 -04:00
Katherine Parry	4177f4f148	Updated FMA	2021-06-14 13:42:53 -04:00
James E. Stine	11c88c15d5	Put repository of fpdivsqrt with RTL-based adder instead of structural implementation	2021-06-11 14:35:22 -04:00
Katherine Parry	0acf665a8b	lint is clean	2021-06-07 14:22:54 -04:00
Katherine Parry	75a6097467	fixed lint warnings for fpu and lzd	2021-06-05 12:06:33 -04:00
Katherine Parry	fc65aedbd6	Double-precision FMA instructions	2021-06-04 14:00:11 -04:00
Ross Thompson	e50a1ef5e4	Fixed a few lint errors, ... clock gater was wrong, missing signal definitions in branch predictor.	2021-06-02 09:33:24 -05:00
James E. Stine	564d7c4adb	Minor cosmetic update to fpu.sv	2021-06-01 15:45:32 -04:00
Ross Thompson	fe22fd2db8	added clock gater to floating point divider to speed up simulation time.	2021-06-01 13:46:21 -05:00
Katherine Parry	778ba6bbf5	classify unit created and passes imperas tests	2021-05-27 18:53:55 -04:00
Katherine Parry	1459d840ed	All compare instructions pass imperas tests	2021-05-27 15:23:28 -04:00
Katherine Parry	309e6c3dc1	FADD and FSUB imperas tests pass	2021-05-26 12:33:33 -04:00
James E. Stine	bb99480fca	delete old file for FPregfile	2021-05-26 09:13:09 -05:00
James E. Stine	77260643eb	Add regression test for fpadd	2021-05-26 09:12:37 -05:00
Katherine Parry	e7190b0690	renamed top level FPU wires	2021-05-25 20:04:34 -04:00
James E. Stine	bb5404e14a	Update FPregfile to use more compact code and better structure for ease in reading	2021-05-25 13:21:59 -05:00
Katherine Parry	90d5fdba04	FMV.X.D imperas test passes	2021-05-24 14:44:30 -04:00
James E. Stine	6f38b7633c	Update header for FPadd	2021-05-24 08:28:16 -05:00
Katherine Parry	70968a4ec3	FSD and FLD imperas tests pass	2021-05-23 18:33:14 -04:00
Katherine Parry	06af239e6c	FMV.D.X imperas test passes	2021-05-20 22:17:59 -04:00
Katherine Parry	9464c9022d	floating point infinite loop removed from imperas tests	2021-05-18 10:42:51 -04:00
Katherine Parry	ff5a809c26	fpu warnings fixed/commented	2021-05-03 19:17:09 +00:00