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4,094 Commits 4 Branches 2 Tags 53 MiB
03e731b3ff
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91 Commits

Author SHA1 Message Date
David Harris
03e731b3ff Set correct size of IROM/DTIM and allow FLEN>XLEN with DTIM 2022-08-26 21:05:20 -07:00
David Harris
812158aeee Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each 2022-08-26 20:26:12 -07:00
David Harris
95dd50a567 Renamed DMEM to DTIM and added checks about compatibility of DTIM/IROM and virtmem 2022-08-26 20:12:03 -07:00
Ross Thompson
db635e3ad2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-25 16:01:02 -05:00
David Harris
302a7fa294 Extended HADDR to PA_BITS 2022-08-25 13:11:36 -07:00
Ross Thompson
179aec3616 Still not working with rv32ic. 2022-08-25 15:03:54 -05:00
Ross Thompson
3b612d6201 Possible fixes for earily messup of rv32ic and rv64ic configs. 2022-08-25 14:42:08 -05:00
Ross Thompson
e605ef57dc BROKEN. Don't use this commit. 
Issue running cacheless with bus.
 2022-08-25 11:02:46 -05:00
Ross Thompson
b0aea77b20 Added generate around uncore. 2022-08-25 10:35:24 -05:00
Ross Thompson
769af32f2a Renamed RAM to UNCORE_RAM. 2022-08-24 18:09:07 -05:00
Ross Thompson
fc22e807e2 Merged testbench-fpga into testbench. 
Modified SDC to simplify LimitTimers.  LimitTimers needs to be 0 for implmementation and 1 for simulation.
 2022-08-24 17:52:25 -05:00
Ross Thompson
4a371b6829 added SD card and external ram to common testbench. 2022-08-24 13:27:18 -05:00
Ross Thompson
51adf6cba9 Modified the lsu/ifu memory configurations. 2022-08-24 12:35:15 -05:00
David Harris
7fcc852687 Q depends on D 2022-08-23 08:29:59 -07:00
David Harris
e714b75888 LSU minor edits 2022-08-23 07:35:47 -07:00
David Harris
16a92eaf10 Updated testbench assertions. 2022-08-23 07:23:24 -07:00
David Harris
75a265159b Increased timeout threshold to avoid timeout building riscof tests on slow machine 2022-07-27 04:05:21 +00:00
David Harris
9ecef0c4cd fixed testbench merge comflict 2022-07-26 06:21:46 -07:00
David Harris
2d7f4b133c More work toward riscof tests 2022-07-26 06:19:13 -07:00
David Harris
5c54c5b521 Added rv32f tests to RV64gc 2022-07-25 23:29:05 +00:00
Ross Thompson
8193946996 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-23 08:41:59 -05:00
Daniel Torres
95fdd408ee commiting current changes to riscof wally tests 2022-07-22 11:14:04 -07:00
Katherine Parry
7268b4b334 removed underflow from inexactct calculation 2022-07-18 17:51:18 +00:00
Ross Thompson
0ef6137ab9 Added degree of freedom to cache/sram. The sram width in bits is no longer defined by XLEN, but instead a separate parameter. This is decoupled from LINELEN, XLEN, and WORDLEN. 2022-07-17 21:05:31 -05:00
Ross Thompson
8356e5d742 Updated cache sram's to use 1 sram for all words in a way. Still needs to modified to support subdivision by max physical sram width. 2022-07-17 16:20:04 -05:00
Katherine Parry
18d7fee541 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-12 22:37:20 +00:00
DTowersM
fe7d03a3da added some preliminary support for coremark XLEN=32, made sure rv64 not impacted 2022-07-11 21:13:09 +00:00
Katherine Parry
97e7e619d9 moved fpu ieu write data mux to lsu 2022-07-08 23:56:57 +00:00
David Harris
8be1dafbd6 Removed testbench code that ignores mismatch on zero signatures 2022-07-08 09:17:31 +00:00
David Harris
f865994ba1 fixing port errors 2022-07-07 21:57:10 +00:00
David Harris
f5bdbbe219 Removed sig4 spurious message from testbench 2022-07-05 03:27:14 +00:00
Daniel Torres
2ae22ac6cb added changes to testbench, tests and riscof for additional riscof compatability 2022-06-29 12:23:40 -07:00
slmnemo
80a57d0469 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-21 02:16:26 -07:00
slmnemo
b2cea45de0 Added rudimentary GPIO test according to testplans in chapter 15 2022-06-21 02:16:21 -07:00
Katherine Parry
03d823f5d7 added fld in rv32 - needs testing 2022-06-20 22:53:13 +00:00
Daniel Torres
397783812d embench and testbench now support running both O2 and Os build variations without overwriting one another 2022-06-17 21:15:42 -07:00
Daniel Torres
1d4c543f71 arch tests now run on spike and sail and compare signatures during build 2022-06-17 20:53:15 -07:00
Daniel Torres
0ede7c412e removed old code from makefile, simplified code in testbench 2022-06-17 15:13:38 -07:00
Daniel Torres
475220a5ff arch bug fixes and testbench changes 2022-06-17 15:07:16 -07:00
Katherine Parry
5f7072bd96 postprocessing unit created and passing all tests 2022-06-13 22:47:51 +00:00
slmnemo
a5aa75e5de Merge branch 'main' into cacheburstmode 2022-06-08 02:21:33 +00:00
DTowersM
1d41e98504 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-07 23:58:58 +00:00
DTowersM
3d654fd481 modified testbench.sv- now works with coremark 2022-06-07 23:58:50 +00:00
DTowersM
930c806753 cleaned up the <begin_signature> code, now works for code bases larger than 0x10000000 2022-06-07 23:27:54 +00:00
DTowersM
4cadf139a6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-07 06:03:19 +00:00
DTowersM
fbfae61ba8 added support for 64 bit rv tests 2022-06-07 06:02:23 +00:00
DTowersM
23d524b439 testbench now reads begin_signature addr from .objdump.addr instead of from tests.vh 2022-06-03 22:07:14 +00:00
David Harris
9cd6b309b4 Cleaned up test cases in testbench 2022-06-02 08:44:28 -07:00
DTowersM
d3c8ee7154 added support for embench post processing to testbench.sv 2022-06-01 21:00:44 +00:00
DTowersM
2088c0cd7c added testbench.sv support for embench tests, test output still WIP 2022-05-31 20:13:32 +00:00