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Author SHA1 Message Date
Limnanthes Serafini
034c289a36 Misc typo and indent fixing. 2023-04-13 16:54:15 -07:00
Limnanthes Serafini
7d274eae74 Fix of InvalDelayed warning 2023-04-13 16:53:36 -07:00
Limnanthes Serafini
3f9a22e8d4 Minor comments. 2023-04-12 02:57:42 -07:00
Limnanthes Serafini
095f3d5542 Added performance and distribution to sim and wrapper. Added colors too! 2023-04-12 02:54:05 -07:00
Limnanthes Serafini
65d29306ef Merge branch 'openhwgroup:main' into cachesim 2023-04-12 01:34:45 -07:00
Ross Thompson
18ad6455d0 Merge pull request #232 from stineje/main 
Mod testing for TestFloat
 2023-04-11 23:22:59 -05:00
James Stine
744e170be3 Add feature in testfloat.do to elect wave or nowave 2023-04-11 22:35:04 -05:00
James Stine
811004ef9f Update testbench-fp to run TestFloat for all FP operations 2023-04-11 22:16:20 -05:00
Limnanthes Serafini
a6545a0f47 Logger significantly improved. 2023-04-11 19:29:51 -07:00
Limnanthes Serafini
e5ead0f5b8 Minor logic cleanup (will elaborate in PR) 2023-04-11 19:29:39 -07:00
Limnanthes Serafini
e6a9d236b5 Wrapper for running CacheSim on the rv64gc suites 2023-04-11 19:29:05 -07:00
Limnanthes Serafini
926ec56e18 Cleanup + success message added to CacheSim 2023-04-11 19:28:28 -07:00
David Harris
0eb2511c35 Merge pull request #231 from kipmacsaigoren/priv-tests 
Priv tests Updates for SVADU, and SAIL
 2023-04-11 19:07:13 -07:00
Kip Macsai-Goren
34200e8c76 restored original virt mem tests when svadu is not supported 2023-04-11 18:47:08 -07:00
Kip Macsai-Goren
c4766c8a02 renamed virt mem tests to include svadu 2023-04-11 18:46:37 -07:00
Kip Macsai-Goren
b2d6084eea removed unnecessary 'deadbeef's at the end of reference outputs 2023-04-11 18:32:04 -07:00
Kip Macsai-Goren
a82c0a7780 Modified virt mem tests to do correct r/w when svadu is enabled 2023-04-11 18:08:30 -07:00
Kip Macsai-Goren
4aed880757 enabled SVADU for rv32/64gc 2023-04-11 17:42:26 -07:00
Kip Macsai-Goren
e0b938b409 Removed Trap outputs from writes covered by SVADU 2023-04-11 17:41:57 -07:00
Kip Macsai-Goren
a899606c2b Removed Sail from virt mem tests due to sail not recognizing SVADU 2023-04-11 17:41:31 -07:00
Kip Macsai-Goren
19305fe60a Added sail simulation to priv tests that support it 2023-04-11 13:26:59 -07:00
David Harris
83f5005738 Merge pull request #230 from ACWright256/main 
Excluded coverage for misaligned instructions
 2023-04-11 05:21:09 -07:00
Alexa Wright
fb517163f5 Excluded coverage for misaligned instructions 2023-04-10 23:18:25 -07:00
David Harris
90c9f29beb Merge pull request #226 from SydRiley/main 
Increased coverage for the fpu by adding directed tests to toggle signals
 2023-04-09 21:52:11 -07:00
David Harris
adcc22de9d Merge pull request #223 from ross144/main 
Solves issue 172
 2023-04-09 20:30:26 -07:00
David Harris
23380f343d Merge pull request #224 from kbox13/my-single-change 
Create new PMP tests
 2023-04-09 20:29:03 -07:00
Kevin Box
59e7c9371a Create new pmp tests 
configures all pmpcfg registers in each different address range.
 2023-04-09 16:29:57 -07:00
Sydeny
f4caa62efc Increasing coverage for the fpu by adding directed tests to toggle signals 2023-04-09 13:33:12 -07:00
Ross Thompson
009a020c88 Updated wally figure again to increase resolution. 2023-04-09 12:26:15 -05:00
Ross Thompson
1534ae1879 Updated wally top level figure to fix issue 172. 2023-04-09 12:20:43 -05:00
Ross Thompson
81074a822a Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-09 12:19:44 -05:00
David Harris
c197739841 Merge pull request #222 from kjprime/main 
Remove unnecessary check from compressed instruction decode
 2023-04-09 04:56:21 -07:00
David Harris
df2943b9c1 Merge pull request #221 from dherreravicioso/main 
Added test coverage for Privilege Unit in CSRs
 2023-04-09 04:54:36 -07:00
Kevin Thomas
f7838b869b Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-08 22:56:20 -05:00
Diego Herrera Vicioso
5f9c443781 Added test coverage for floating point registers, some PMP addresses, as well as MTVAL and MCAUSE CSRs. 2023-04-08 16:40:36 -07:00
Ross Thompson
ba08c39eef Merge pull request #220 from davidharrishmc/dev 
Obscure coverage fixes
 2023-04-08 10:27:31 -05:00
David Harris
1c47221983 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-07 21:57:18 -07:00
David Harris
7affe2bdca Waived coverage on BTB memory with byte write enables tied high 2023-04-07 21:56:49 -07:00
David Harris
2f4074b9c2 Improved RAS predictor coverage by eliminating unreachable StallM term 2023-04-07 21:37:12 -07:00
Ross Thompson
cfab7c8b45 Merge pull request #219 from davidharrishmc/dev 
Spill logic coverage and fdivsqrt cleanup
 2023-04-07 23:30:52 -05:00
David Harris
5cdd3d57c7 Commented WFI non-flush in writeback stage of hazard unit 2023-04-07 21:27:13 -07:00
David Harris
b27199e276 Added vm64check tests to cover IMMU vm64 2023-04-07 21:14:52 -07:00
David Harris
0d2de13990 Fixed csrwrites.S to agree with ImperasDV. Now coverage tests pass iter-elf 2023-04-07 21:11:01 -07:00
David Harris
bf9db11a57 Fixed priv.S to initialize stimecmp and agree with ImperasDV 2023-04-07 20:44:01 -07:00
David Harris
9394389fec Bug fix: MTIME & MTIMEH registers are unimplemented and should fault when accessed 2023-04-07 20:43:28 -07:00
David Harris
16eca598ba Fixed WALLY-init-lib to return correctly even from traps from compressed instructions 2023-04-07 20:24:33 -07:00
David Harris
a49f1f785e Fixed enabling machine timer interrupt 2023-04-06 22:18:33 -07:00
David Harris
8ef9891e46 vm64 tests 2023-04-06 21:42:47 -07:00
David Harris
19c39628fa Division cleanup 2023-04-06 21:42:34 -07:00
David Harris
6db65f30b1 Simplified integer division preprocessing in fdivsqrt 2023-04-06 16:43:28 -07:00