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Author SHA1 Message Date
Ross Thompson
d3b2e331c2 Added comments about why it is not possible to use FlushWay and VictimWay directly. 2022-12-09 17:07:35 -06:00
Ross Thompson
f09b9e1572 Finished merge of kip and ross's ifu fix. 2022-12-09 16:52:22 -06:00
Ross Thompson
981ac3963a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-09 16:42:16 -06:00
Ross Thompson
1a24e7029f Minor simplification of cacheway way selection muxes. 2022-12-09 16:42:05 -06:00
Kip Macsai-Goren
055ca9ee37 Addded fix for 32 bit periph test and added test to regression 2022-12-06 09:56:08 -08:00
Ross Thompson
9dd0d66ab5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-06 10:38:14 -06:00
Ross Thompson
5dbcf8fb10 Fixed bug Kip found. 
The no cache and no bus versions lacked assignment of CacheCommittedF in the IFU.
 2022-12-06 10:37:45 -06:00
Kip Macsai-Goren
55627f40e2 added passing GPIO test to 64 bit tests 2022-12-05 21:31:00 -08:00
Kip Macsai-Goren
c6662933c4 commented out periph test from wally32 periph so rv32ic doesn't hang 2022-12-05 20:23:16 -08:00
Kip Macsai-Goren
4c81b6fa5f added corrrect scr read out of uart to periph test 2022-12-05 20:16:02 -08:00
Kip Macsai-Goren
4e2f4855e6 added passing tests to regression 2022-12-05 20:16:02 -08:00
Kip Macsai-Goren
4ab99904a4 added all 32 bit tests to 64 bit periph tests except gpio 2022-12-05 20:16:02 -08:00
Kip Macsai-Goren
51e78d9e48 added copies of 64 bit tests to 32 bit periph and priv tests 2022-12-05 20:16:02 -08:00
Kip Macsai-Goren
540d6c2f41 added -01 to all WALLY tests 2022-12-05 20:16:02 -08:00
Ross Thompson
1a9c932157 Renamed SelBusBuffer to SelFetchBuffer. 2022-12-05 17:51:13 -06:00
Ross Thompson
92066f81b6 Removed commented code. 2022-12-05 17:21:56 -06:00
Ross Thompson
4b30712cb2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-05 17:20:12 -06:00
Ross Thompson
37551ecc43 Renamed VictimTag to just Tag. Tag is used for both the victim and flush tags. 2022-12-05 17:19:51 -06:00
rachanaerra
10ff69efc1 updated constraints file 2022-12-05 15:05:21 -06:00
Ross Thompson
dc31add951 Cache signal renames. 2022-12-04 16:09:09 -06:00
Ross Thompson
9bf0eedf73 Optimized way selection logic. 2022-12-04 12:30:56 -06:00
Ross Thompson
a130a96b45 Found possible optimization as the way selection is shared in cache, cacheway, and cachelru. 2022-12-04 01:20:51 -06:00
Ross Thompson
3dea04e644 Moved selectedway mux into cacheway. It makes way more sense there. 2022-12-04 01:15:47 -06:00
Ross Thompson
f557150cae Rename LineByteMux to FetchbufferbyteSel. 2022-12-04 01:00:04 -06:00
Ross Thompson
fc05e27416 Updated riscv arch test removed misaligned1. 2022-12-04 00:18:10 +00:00
Ross Thompson
350fdd944d Revert "Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider." 
This reverts commit fb221d7b64.
 2022-12-04 00:01:58 +00:00
Ross Thompson
87ce09f7d9 Removed old flow directory. 2022-12-03 10:28:39 -06:00
Ross Thompson
45bc732b4d removed imperas-riscv-tests-deleteme 2022-12-03 00:18:42 +00:00
Ross Thompson
d8fdc179f1 removed unusedsrc directory as it was large 384MB! 2022-12-02 17:37:06 -06:00
Ross Thompson
ae4c36936d Removed design ware mult. 2022-12-02 16:51:12 -06:00
cturek
fb221d7b64 Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider. 2022-12-02 21:44:29 +00:00
cturek
04ac350a29 Added flops to preproc 2022-12-02 20:31:08 +00:00
David Harris
3a07d56d33 Renamed FPUStallD to FCvtIntStallD 2022-12-02 11:55:23 -08:00
David Harris
1b0f878c16 Renamed DivStartE to IFDivStartE 2022-12-02 11:30:49 -08:00
David Harris
db5f3c15a4 FPU divider working with execute stage stall 2022-12-02 11:11:53 -08:00
David Harris
a86c9de36b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-02 04:28:50 -08:00
David Harris
6079a01bc8 update test list 2022-12-02 04:28:47 -08:00
Ross Thompson
602d191580 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-01 22:36:07 -06:00
David Harris
7c3e8553d1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-01 16:27:36 -08:00
David Harris
0d23ab3ec1 reorder tests 2022-12-01 16:27:33 -08:00
Ross Thompson
3442b04f9e Properly flush cacheLRU. 2022-12-01 17:32:58 -06:00
David Harris
3a8602523e FPU test list 2022-12-01 10:18:36 -08:00
Ross Thompson
e403800ce8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-01 11:47:54 -06:00
Ross Thompson
5025664cb0 Removed unused port on cacheway. 2022-12-01 11:47:48 -06:00
David Harris
28996d0b12 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-01 08:15:51 -08:00
David Harris
1bd639be6d code cleanup 2022-12-01 08:15:48 -08:00
Ross Thompson
e6bd86f4fa Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-30 17:19:04 -06:00
David Harris
4ddc8fd603 signal sufixes in integer division 2022-11-30 15:15:37 -08:00
Ross Thompson
fa22484cfe Reverted the IROM/DTIM address range modelsim assignment. 2022-11-30 17:13:33 -06:00
Ross Thompson
2f582cd91f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-30 13:30:37 -06:00