Kip Macsai-Goren
0281330fe8
Merge remote-tracking branch 'upstream/main' into main
2023-02-01 21:31:57 -08:00
Kip Macsai-Goren
f126d1e0ef
added beginning of a ZBS instruction module to the ALU. Control signals still needed
2023-02-01 21:31:25 -08:00
James Stine
fc5692629a
Update ram2 and other memories and associated wrappers
2023-02-01 17:03:48 -06:00
David Harris
ce82d8d550
Fixed merge conflict to get synthesis working again
2023-02-01 04:43:57 -08:00
Madeleine Masser-Frye
57b35c293d
added memories (not tested)
2023-02-01 06:08:27 +00:00
David Harris
5d7dcfb748
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-01-31 14:40:19 -08:00
Ross Thompson
7166fcd4d2
Updates to RAS.
2023-01-31 15:17:32 -06:00
Ross Thompson
dd556e8763
Simplified RAS.
2023-01-31 14:54:05 -06:00
Ross Thompson
122809b2b2
RAS file name was spelled wrong.
2023-01-31 14:35:05 -06:00
Ross Thompson
0678e70b4b
Merge branch 'imperas'
2023-01-31 12:46:22 -06:00
Ross Thompson
52bdf32575
Minor bug fix in gshare.
2023-01-31 10:45:32 -06:00
Ross Thompson
e7b91d5934
Renamed signals in RAS.
2023-01-31 10:44:11 -06:00
Ross Thompson
b4854d8e94
Found small bug in gshare.
2023-01-31 00:17:49 -06:00
Ross Thompson
b64b3016e2
Parameterized testbench branch predictor preload.
2023-01-31 00:08:11 -06:00
Ross Thompson
22ef051603
More branch predictor cleanup.
2023-01-30 23:55:52 -06:00
Ross Thompson
61759af9dc
Improved signal names.
2023-01-30 23:51:04 -06:00
Ross Thompson
165b4858d7
Major cleanup of branch predictor.
2023-01-30 23:37:34 -06:00
Ross Thompson
57ab5a7488
Simplified gshare.
2023-01-30 19:27:18 -06:00
Ross Thompson
0e29a5f9c2
Minor gshare optimization.
2023-01-30 18:13:12 -06:00
David Harris
6777fd9b55
Restored top-level modules without import statements
2023-01-30 12:54:40 -08:00
David Harris
49e45f45b7
Moved out version of wally using package because synthesis isn't working yet
2023-01-30 12:48:52 -08:00
David Harris
1e7c9f026c
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-01-30 11:00:51 -08:00
Ross Thompson
7a4218788c
Imperas found a real bug in virtual memory.
...
If the instruction address spilled across two pages and the second page misses the TLB,
the HPTW received a tlb miss at the address of the first page rather than the second.
After the walk the TLB was updated with the PTE from the first page at the address of the
second page.
Example bug
Instruction PCF = 0x2ffe
First page in 0x2ffe and second page in 0x3000.
The second page misses the TLB and generates HPTW request at 0x2ffe rather than 0x3000.
TLB is updated with PTE from 0x2ffe at 0x3000.
2023-01-30 11:47:51 -06:00
Ross Thompson
63267ff378
optimized branch predictor by removing unnecessary registers.
2023-01-29 22:39:37 -06:00
Ross Thompson
dd9d2be89c
Updated global history branch predictcor with the gshare improvements.
2023-01-29 16:26:44 -06:00
David Harris
7705209141
Merged PR#37 branch predictor
2023-01-29 14:25:28 -08:00
David Harris
db07c6618b
Removed unused TESTSBP parameter
2023-01-29 14:19:24 -08:00
Ross Thompson
a9902337cf
Merge branch 'main' of https://github.com/openhwgroup/cvw
...
This merges the branch predictor improvements into the main repo.
2023-01-29 15:24:20 -06:00
Ross Thompson
7c8b2b685f
gshare cleanup.
2023-01-29 15:07:45 -06:00
Ross Thompson
2a336cfb71
Gshare cleanup.
2023-01-29 15:06:35 -06:00
Ross Thompson
244885d3fa
Found bug in gshare.
2023-01-29 15:03:25 -06:00
David Harris
a099cbb45b
Fixed configuration of ram to use macro when depth is corret
2023-01-29 11:35:17 -08:00
Ross Thompson
c8df460b28
Fixed bug with the btb's valid bit not beind held on a stall.
2023-01-29 00:49:23 -06:00
Ross Thompson
9e3074689d
Fixed another bug with the speculative gshare with instruction class prediction.
2023-01-29 00:33:40 -06:00
David Harris
799caef2c9
Renamed BPTYPE to BPRED_TYPE
2023-01-28 20:06:12 -08:00
David Harris
b89fe9989e
Renamed DCACHE to DCACHE_SUPPORTED and ICACHE to ICACHE_SUPPORTED
2023-01-28 18:52:00 -08:00
David Harris
fa3643a064
Renamed BUS to BUS_SUPPORTED
2023-01-28 18:35:53 -08:00
David Harris
8a96dcf0ae
Config cleanup and renamed BPRED_ENABLED to BPRED_SUPPORTED
2023-01-28 18:17:42 -08:00
David Harris
c73fe4041e
Fixed typo in ram2p1r1wbe_1024x69 and renamed for consistency
2023-01-28 18:07:33 -08:00
David Harris
e27ab1a052
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-01-28 17:55:08 -08:00
James Stine
5a0d8aed23
Modified changes as follows
...
* Add docs directory for Docker including Dockerfile
* Change to synthesis script to include fpu stuff
* Add wrappers for IP (may need some cleanup but will cleanup shortly)
2023-01-28 19:33:00 -06:00
Ross Thompson
6945eaf045
Fixed bug with the new csr.
2023-01-28 17:56:56 -06:00
Ross Thompson
684a7214cb
Added another performance counter to track overall branch miss-predictions.
2023-01-28 17:50:46 -06:00
Ross Thompson
3ddf95ac6e
Found an issue where the btb was not forwarding the valid bit!
2023-01-28 17:00:50 -06:00
Ross Thompson
b52990e2ce
Possible workign instruction class prediction repair.
2023-01-28 16:42:19 -06:00
Ross Thompson
3f25123c63
Possible fix for speculative gshare.
2023-01-28 16:14:19 -06:00
David Harris
ed1aaa6c8f
Comment cleanup in subcachelineread
2023-01-28 11:00:05 -08:00
David Harris
1b0b9314c4
removed unused memory model
2023-01-28 10:58:36 -08:00
David Harris
6c59c21a26
Updated cvw to be consistent with configs
2023-01-28 10:58:02 -08:00
David Harris
eeaa5d9982
Removed unneeded lint directive from core
2023-01-27 15:48:30 -08:00
