162 Commits

Author	SHA1	Message	Date
David Harris	38b8cc652c	All tests passing with bus interface	2021-02-24 07:25:03 -05:00
Ross Thompson	c856003f73	RAS needs to be reset or preloaded. For now I just reset it. ... Fixed bug with the instruction class. Most tests now pass. Only Wally-JAL and the compressed instruction tests fail. Currently the bpred does not support compressed. This will be in the next version.	2021-02-19 20:09:07 -06:00
Ross Thompson	bbe0db3ebe	Integrated the branch predictor into the hardward. Not yet working.	2021-02-17 22:19:17 -06:00
David Harris	adc5d5bc1a	Added MUL	2021-02-15 22:27:35 -05:00
David Harris	842c374de9	Debugging instruction fetch	2021-02-09 11:02:17 -05:00
David Harris	33110ed636	Data memory bus integration	2021-02-07 23:21:55 -05:00
David Harris	429f48e766	Rename ifu/dmem/ebu signals to match uarch diagram	2021-02-02 15:09:24 -05:00
David Harris	616830a3f0	Cleaned up hazard interface	2021-02-02 13:53:13 -05:00
David Harris	bb83fda1d8	Moved writeback pipeline registers from datapth into DMEM and CSR	2021-02-02 13:02:31 -05:00
David Harris	92bf1674b4	Moved fpu to temporary location to fix compile and cleaned up interface formatting	2021-02-01 23:44:41 -05:00
David Harris	1a3963bed0	Renamed DCU to DMEM	2021-02-01 18:52:22 -05:00
David Harris	07af481b67	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00