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Removed unnecessary generate inside hptw

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This commit is contained in:
David Harris 2021-12-30 21:21:00 +00:00
parent 25c634da8b
commit ffc2a2097a
2 changed files with 267 additions and 276 deletions
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1
wally-pipelined/src/lsu/lsu.sv
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@ -268,7 +268,6 @@ module lsu
endgenerate endgenerate
// conditional // conditional
// 1. ram // controlled by `MEM_DTIM // 1. ram // controlled by `MEM_DTIM
// 2. cache `MEM_DCACHE // 2. cache `MEM_DCACHE

8
wally-pipelined/src/mmu/hptw.sv
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@ -54,8 +54,6 @@ module hptw
L3_ADR, L3_RD, L3_ADR, L3_RD,
LEAF, IDLE} statetype; // *** placed outside generate statement to remove synthesis errors LEAF, IDLE} statetype; // *** placed outside generate statement to remove synthesis errors
generate
if (`MEM_VIRTMEM) begin:virtmem
logic DTLBWalk; // register TLBs translation miss requests logic DTLBWalk; // register TLBs translation miss requests
logic [`PPN_BITS-1:0] BasePageTablePPN; logic [`PPN_BITS-1:0] BasePageTablePPN;
logic [`PPN_BITS-1:0] CurrentPPN; logic [`PPN_BITS-1:0] CurrentPPN;
@ -200,10 +198,4 @@ module hptw
NextWalkerState = IDLE; // should never be reached NextWalkerState = IDLE; // should never be reached
end end
endcase endcase
end else begin // No Virtual memory supported; tie HPTW outputs to 0
assign HPTWRead = 0;
assign HPTWAdr = 0;
assign HPTWSize = 3'b000;
end
endgenerate
endmodule endmodule