From ffb248dc656f08cc9cd0a3f4ecf13b112e9b93fb Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 5 Jul 2024 21:32:57 -0700 Subject: [PATCH] Fixed issue 868 about tlbmisc.S coverage test failing due to HPTW writing wrong address when updateing A bit --- src/mmu/hptw.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index da56a21a0..7a0d2c4a6 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -172,7 +172,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( mux2 #(P.XLEN) NextPTEMux(ReadDataM, AccessedPTE, UpdatePTE, NextPTE); // NextPTE = ReadDataM when ADUE = 0 because UpdatePTE = 0 flopenr #(P.PA_BITS) HPTWAdrWriteReg(clk, reset, SaveHPTWAdr, HPTWReadAdr, HPTWWriteAdr); - assign SaveHPTWAdr = WalkerState == L0_ADR; + assign SaveHPTWAdr = (NextWalkerState == L0_RD | NextWalkerState == L1_RD | NextWalkerState == L2_RD | NextWalkerState == L3_RD); // save the HPTWAdr when the walker is about to read the PTE at any level; the last level read is the one to write during UpdatePTE assign SelHPTWWriteAdr = UpdatePTE | HPTWRW[0]; mux2 #(P.PA_BITS) HPTWWriteAdrMux(HPTWReadAdr, HPTWWriteAdr, SelHPTWWriteAdr, HPTWAdr);