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Finished up testbench reformatting

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Limnanthes Serafini 2023-04-13 19:18:26 -07:00
parent b9c97c6a8c
commit ff72cbc1b2
1 changed files with 59 additions and 58 deletions
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testbench/testbench.sv
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@ -560,7 +560,8 @@ module testbench;
int file; int file;
string LogFile; string LogFile;
logic resetD, resetEdge; logic resetD, resetEdge;
logic Enable, InvalDelayed; logic Enable;
logic InvalDelayed, InvalEdge;
assign Enable = dut.core.ifu.bus.icache.icache.cachefsm.LRUWriteEn & assign Enable = dut.core.ifu.bus.icache.icache.cachefsm.LRUWriteEn &
dut.core.ifu.immu.immu.pmachecker.Cacheable & dut.core.ifu.immu.immu.pmachecker.Cacheable &