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Fixed another bug with virtual memory and no caches.

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This commit is contained in:
Rose Thompson 2024-01-18 09:29:52 -06:00
parent e8474373e4
commit ff6bb3be0c
1 changed files with 5 additions and 1 deletions
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6
src/lsu/lsu.sv
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@ -111,6 +111,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
logic GatedStallW; // Hazard unit StallW gated when SelHPTW = 1 logic GatedStallW; // Hazard unit StallW gated when SelHPTW = 1
logic BusStall; // Bus interface busy with multicycle operation logic BusStall; // Bus interface busy with multicycle operation
logic LSUBusStallM; // Bus interface busy with multicycle operation masked by IgnoreRequestTLB
logic HPTWStall; // HPTW busy with multicycle operation logic HPTWStall; // HPTW busy with multicycle operation
logic DCacheBusStallM; // Cache or bus stall logic DCacheBusStallM; // Cache or bus stall
logic CacheBusHPWTStall; // Cache, bus, or hptw is requesting a stall logic CacheBusHPWTStall; // Cache, bus, or hptw is requesting a stall
@ -226,7 +227,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
// the trap module. // the trap module.
assign CommittedM = SelHPTW | DCacheCommittedM | BusCommittedM; assign CommittedM = SelHPTW | DCacheCommittedM | BusCommittedM;
assign GatedStallW = StallW & ~SelHPTW; assign GatedStallW = StallW & ~SelHPTW;
assign DCacheBusStallM = DCacheStallM | BusStall; assign DCacheBusStallM = DCacheStallM | LSUBusStallM;
assign CacheBusHPWTStall = DCacheBusStallM | HPTWStall; assign CacheBusHPWTStall = DCacheBusStallM | HPTWStall;
assign LSUStallM = CacheBusHPWTStall | SpillStallM; assign LSUStallM = CacheBusHPWTStall | SpillStallM;
@ -354,6 +355,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
.Cacheable(CacheableOrFlushCacheM), .BusRW, .Stall(GatedStallW), .Cacheable(CacheableOrFlushCacheM), .BusRW, .Stall(GatedStallW),
.BusStall, .BusCommitted(BusCommittedM)); .BusStall, .BusCommitted(BusCommittedM));
// Mux between the 3 sources of read data, 0: cache, 1: Bus, 2: DTIM // Mux between the 3 sources of read data, 0: cache, 1: Bus, 2: DTIM
// Uncache bus access may be smaller width than LLEN. Duplicate LLENPOVERAHBW times. // Uncache bus access may be smaller width than LLEN. Duplicate LLENPOVERAHBW times.
// *** DTIMReadDataWordM should be increased to LLEN. // *** DTIMReadDataWordM should be increased to LLEN.
@ -388,6 +390,8 @@ module lsu import cvw::*; #(parameter cvw_t P) (
assign {DCacheStallM, DCacheCommittedM} = '0; assign {DCacheStallM, DCacheCommittedM} = '0;
end end
assign LSUBusStallM = BusStall & ~IgnoreRequestTLB;
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
// Atomic operations // Atomic operations
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////