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	Return testbench to normal
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				| @ -56,13 +56,13 @@ module testbench(); | ||||
| //                    "rv64m/I-REMW-01", "3000"
 | ||||
|   }; | ||||
|   string tests64ic[] = '{ | ||||
|                      "rv64ic/I-C-BEQZ-01", "3000", | ||||
|                      "rv64ic/I-C-ADD-01", "3000", | ||||
|                      "rv64ic/I-C-ADDI-01", "3000", | ||||
|                      "rv64ic/I-C-ADDIW-01", "3000", | ||||
|                      "rv64ic/I-C-ADDW-01", "3000", | ||||
|                      "rv64ic/I-C-AND-01", "3000", | ||||
|                      "rv64ic/I-C-ANDI-01", "3000", | ||||
|                      "rv64ic/I-C-BEQZ-01", "3000", | ||||
|                      "rv64ic/I-C-BNEZ-01", "3000", | ||||
|                      "rv64ic/I-C-EBREAK-01", "2000", | ||||
|                      "rv64ic/I-C-J-01", "3000", | ||||
| @ -327,7 +327,7 @@ string tests32i[] = { | ||||
|       if (`C_SUPPORTED) tests = {tests64ic, tests}; | ||||
|       else              tests = {tests, tests64iNOc}; | ||||
|       if (`M_SUPPORTED) tests = {tests, tests64m}; | ||||
|       if (`A_SUPPORTED) tests = {tests64a, tests}; | ||||
|       if (`A_SUPPORTED) tests = {tests, tests64a}; | ||||
|  //     tests = {tests64a, tests};
 | ||||
|     end else begin // RV32
 | ||||
|       tests = {tests32i}; | ||||
|  | ||||
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