Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

pipelined/src/cache/cachefsm.sv

@@ -86,7 +86,7 @@ module cachefsm
   logic               DoAMOMiss, DoReadMiss, DoWriteMiss;
   logic               FlushFlag;
     
-  typedef enum 		  {STATE_READY,
+  typedef enum logic [3:0]		  {STATE_READY,
 
 					   STATE_MISS_FETCH_WDV,
 					   STATE_MISS_FETCH_DONE,

pipelined/src/ebu/ahblite.sv

@@ -35,10 +35,6 @@
 
 `include "wally-config.vh"
 
-package ahbliteState;
-  typedef enum logic [3:0] {IDLE, MEMREAD, MEMWRITE, INSTRREAD} statetype;
-endpackage
-
 module ahblite (
   input logic 				 clk, reset,
   // Load control
@@ -75,6 +71,9 @@ module ahblite (
   (* mark_debug = "true" *) output logic HWRITED
 );
 
+  typedef enum logic [1:0] {IDLE, MEMREAD, MEMWRITE, INSTRREAD} statetype;
+  statetype BusState, NextBusState;
+
   logic GrantData;
   logic [31:0] AccessAddress;
   logic [2:0] ISize;
@@ -88,8 +87,6 @@ module ahblite (
   // Data accesses have priority over instructions.  However, if a data access comes
   // while an instruction read is occuring, the instruction read finishes before
   // the data access can take place.
-  import ahbliteState::*;
-  statetype BusState, NextBusState;
 
   flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextBusState, IDLE, BusState);
 

pipelined/src/ieu/controller.sv

@@ -228,5 +228,5 @@ module controller(
 
   assign CSRWritePendingDEM = CSRWriteD | CSRWriteE | CSRWriteM;
 
-  assign StoreStallD = MemRWE[0] & (|MemRWD | |AtomicD);
+  assign StoreStallD = MemRWE[0] & ((|MemRWD) | (|AtomicD));
 endmodule

pipelined/src/ifu/spillsupport.sv

@@ -65,7 +65,7 @@ module spillsupport (
   
   assign SpillF = &PCF[$clog2(SPILLTHRESHOLD)+1:1];
 
-  typedef enum      {STATE_SPILL_READY, STATE_SPILL_SPILL} statetype;
+  typedef enum logic [1:0]     {STATE_SPILL_READY, STATE_SPILL_SPILL} statetype;
   (* mark_debug = "true" *)  statetype CurrState, NextState;
 
   always_ff @(posedge clk)

pipelined/src/lsu/busfsm.sv

@@ -64,7 +64,7 @@ module busfsm #(parameter integer   WordCountThreshold,
   logic 			   UnCachedAccess;
   
 
-  typedef enum {STATE_BUS_READY,
+  typedef enum logic [2:0] {STATE_BUS_READY,
 				STATE_BUS_FETCH,
 				STATE_BUS_WRITE,
 				STATE_BUS_UNCACHED_WRITE,

pipelined/src/lsu/interlockfsm.sv

@@ -49,7 +49,7 @@ module interlockfsm
    output logic IgnoreRequestTrapM);
 
 
-  typedef enum  {STATE_T0_READY,
+  typedef enum logic[2:0]  {STATE_T0_READY,
 				 STATE_T0_REPLAY,
 				 STATE_T3_DTLB_MISS,
 				 STATE_T4_ITLB_MISS,

pipelined/src/mmu/hptw.sv

@@ -46,7 +46,7 @@ module hptw
    output logic [2:0] 		   HPTWSize // 32 or 64 bit access.
 );
 
-	typedef enum  {L0_ADR, L0_RD, 
+	typedef enum logic [3:0] {L0_ADR, L0_RD, 
 					L1_ADR, L1_RD, 
 					L2_ADR, L2_RD, 
 					L3_ADR, L3_RD, 

pipelined/src/uncore/uartPC16550D.sv

@@ -55,7 +55,7 @@ module uartPC16550D(
 	);
 
   // transmit and receive states // *** neeed to work on synth warning -- it wants to make enums 32 bits by default
-  typedef enum {UART_IDLE, UART_ACTIVE, UART_DONE, UART_BREAK} statetype;
+  typedef enum logic [1:0] {UART_IDLE, UART_ACTIVE, UART_DONE, UART_BREAK} statetype;
 
   // Registers
   logic [10:0] RBR;

synthDC/.synopsys_dc.setup

@@ -12,10 +12,10 @@ if { [info exists ::env(RISCV)] } {
 }
 
 if {$tech == "sky130"} {
-    set s8lib ../addins/sky130_osu_sc_t12/12T_ms/lib/
+    set s8lib $timing_lib/sky130_osu_sc_t12/12T_ms/lib
     lappend search_path $s8lib
 } elseif {$tech == "sky90"} {
-    set s9lib $timing_lib/sky90/tech_files/
+    set s9lib $timing_lib/sky90/sky90_sc/V1.7.4/lib
     lappend search_path $s9lib
 }
 

synthDC/README.md

@@ -16,21 +16,18 @@ FREQ
         Frequency in MHz.  Default is 500
 
 CONFIG
-        The wally configuration file.  Default is rv32e.
+        The Wally configuration file.  The default is rv32e.
-        Examples.
+        Examples: rv32e, rv64gc, rv32gc
-        rv32e
-        rv64gc
-        rv32gc
 
 TECH
-        The target standard cell library.  Default is 130.
+        The target standard cell library.  The default is sky130.
         sky90: skywater 90nm TT 25C
         sky130: skywater 130nm TT 25C
 
 SAIFPOWER
-        Controls if power analysis is driven by switching factor or RTL modelsim simulation.
+        Controls if power analysis is driven by switching factor or
-        When enabled requires a saif file named power.saif.
+	RTL modelsim simulation. When enabled requires a saif file
-        Default is 0.
+	named power.saif.  The default is 0.
         0: switching factor power analysis
         1: RTL simulation driven power analysis.
 

synthDC/scripts/synth.tcl

@@ -3,6 +3,13 @@
 # james.stine@okstate.edu 27 Sep 2015
 #
 
+# Ignore unnecessary warnings:
+# intraassignment delays for nonblocking assignments are ignored
+suppress_message {VER-130} 
+# statements in initial blocks are ignored
+suppress_message {VER-281} 
+suppress_message {VER-173} 
+
 # get outputDir from environment (Makefile)
 set outputDir $::env(OUTPUTDIR)
 set cfgName $::env(CONFIG)