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Removed XEnE, YEnE, and ZEnE from forward logic.

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Cleanup comments.
This commit is contained in:
Ross Thompson 2022-12-23 14:24:20 -06:00
parent af9afafdae
commit fe9361de34
3 changed files with 24 additions and 33 deletions
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27
pipelined/src/fpu/fctrl.sv
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@ -196,26 +196,21 @@ module fctrl (
else if (`FPSIZES == 3|`FPSIZES == 4) else if (`FPSIZES == 3|`FPSIZES == 4)
assign FmtD = ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : Funct7D[1:0]; assign FmtD = ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : Funct7D[1:0];
// Enables indicate that a source register is used and may need stalls. Also indicate special cases for infinity or NaN.
// enables:
// X - all except int->fp, store, load, mv int->fp
// Y - all except cvt, mv, load, class, sqrt
// Z - fma ops only
// Enables indicate that a source register is used and may need forwarding. Also indicate special cases for infinity or NaN.
// When disabled infinity and NaN on source registers are ignored by the unpacker and thus special case logic. // When disabled infinity and NaN on source registers are ignored by the unpacker and thus special case logic.
assign XEnD = ~(((FResSelD==2'b10)&~FWriteIntD)| // load/store // X - all except int->fp, store, load, mv int->fp
((FResSelD==2'b11)&FRegWriteD)| // mv int to float assign XEnD = ~(((FResSelD==2'b10)&~FWriteIntD)| // load/store
((FResSelD==2'b01)&(PostProcSelD==2'b00)&OpCtrlD[2])); // cvt int to float ((FResSelD==2'b11)&FRegWriteD)| // mv int to float
((FResSelD==2'b01)&(PostProcSelD==2'b00)&OpCtrlD[2])); // cvt int to float
assign YEnD = ~(((FResSelD==2'b10)&(FWriteIntD|FRegWriteD))| // load or class // Y - all except cvt, mv, load, class, sqrt
(FResSelD==2'b11)| // mv both ways assign YEnD = ~(((FResSelD==2'b10)&(FWriteIntD|FRegWriteD))| // load or class
((FResSelD==2'b01)&((PostProcSelD==2'b00)|((PostProcSelD==2'b01)&OpCtrlD[0])))); // cvt both or sqrt (FResSelD==2'b11)| // mv both ways
((FResSelD==2'b01)&((PostProcSelD==2'b00)|((PostProcSelD==2'b01)&OpCtrlD[0])))); // cvt both or sqrt
assign ZEnD = (PostProcSelD==2'b10)&(FResSelD==2'b01)&(~OpCtrlD[2]|OpCtrlD[1]); // fma, add, sub // Z - fma ops only
assign ZEnD = (PostProcSelD==2'b10)&(FResSelD==2'b01)&(~OpCtrlD[2]|OpCtrlD[1]); // fma, add, sub
// Final Res Sel: // Final Res Sel:

28
pipelined/src/fpu/fhazard.sv
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@ -37,7 +37,6 @@ module fhazard(
input logic [4:0] RdE, RdM, RdW, // the adress being written to input logic [4:0] RdE, RdM, RdW, // the adress being written to
input logic [1:0] FResSelM, // the result being selected input logic [1:0] FResSelM, // the result being selected
input logic XEnD, YEnD, ZEnD, input logic XEnD, YEnD, ZEnD,
input logic XEnE, YEnE, ZEnE,
output logic FPUStallD, // stall the decode stage output logic FPUStallD, // stall the decode stage
output logic [1:0] ForwardXE, ForwardYE, ForwardZE // select a forwarded value output logic [1:0] ForwardXE, ForwardYE, ForwardZE // select a forwarded value
); );
@ -55,30 +54,27 @@ module fhazard(
ForwardZE = 2'b00; // choose FRD3E ForwardZE = 2'b00; // choose FRD3E
// if the needed value is in the memory stage - input 1 // if the needed value is in the memory stage - input 1
if(XEnE) if ((Adr1E == RdM) & FRegWriteM) begin
if ((Adr1E == RdM) & FRegWriteM) begin // if the result will be FResM (can be taken from the memory stage)
// if the result will be FResM (can be taken from the memory stage) if(FResSelM == 2'b00) ForwardXE = 2'b10; // choose FResM
if(FResSelM == 2'b00) ForwardXE = 2'b10; // choose FResM
// if the needed value is in the writeback stage // if the needed value is in the writeback stage
end else if ((Adr1E == RdW) & FRegWriteW) ForwardXE = 2'b01; // choose FPUResult64W end else if ((Adr1E == RdW) & FRegWriteW) ForwardXE = 2'b01; // choose FPUResult64W
// if the needed value is in the memory stage - input 2 // if the needed value is in the memory stage - input 2
if(YEnE) if ((Adr2E == RdM) & FRegWriteM) begin
if ((Adr2E == RdM) & FRegWriteM) begin // if the result will be FResM (can be taken from the memory stage)
// if the result will be FResM (can be taken from the memory stage) if(FResSelM == 2'b00) ForwardYE = 2'b10; // choose FResM
if(FResSelM == 2'b00) ForwardYE = 2'b10; // choose FResM
// if the needed value is in the writeback stage // if the needed value is in the writeback stage
end else if ((Adr2E == RdW) & FRegWriteW) ForwardYE = 2'b01; // choose FPUResult64W end else if ((Adr2E == RdW) & FRegWriteW) ForwardYE = 2'b01; // choose FPUResult64W
// if the needed value is in the memory stage - input 3 // if the needed value is in the memory stage - input 3
if(ZEnE) if ((Adr3E == RdM) & FRegWriteM) begin
if ((Adr3E == RdM) & FRegWriteM) begin // if the result will be FResM (can be taken from the memory stage)
// if the result will be FResM (can be taken from the memory stage) if(FResSelM == 2'b00) ForwardZE = 2'b10; // choose FResM
if(FResSelM == 2'b00) ForwardZE = 2'b10; // choose FResM
// if the needed value is in the writeback stage // if the needed value is in the writeback stage
end else if ((Adr3E == RdW) & FRegWriteW) ForwardZE = 2'b01; // choose FPUResult64W end else if ((Adr3E == RdW) & FRegWriteW) ForwardZE = 2'b01; // choose FPUResult64W
end end

2
pipelined/src/fpu/fpu.sv
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@ -200,7 +200,7 @@ module fpu (
// Hazard unit for FPU // Hazard unit for FPU
// - determines if any forwarding or stalls are needed // - determines if any forwarding or stalls are needed
fhazard fhazard(.Adr1D, .Adr2D, .Adr3D, .Adr1E, .Adr2E, .Adr3E, .FRegWriteE, .FRegWriteM, .FRegWriteW, .RdE, .RdM, .RdW, .FResSelM, fhazard fhazard(.Adr1D, .Adr2D, .Adr3D, .Adr1E, .Adr2E, .Adr3E, .FRegWriteE, .FRegWriteM, .FRegWriteW, .RdE, .RdM, .RdW, .FResSelM,
.XEnD, .YEnD, .ZEnD, .XEnE, .YEnE, .ZEnE, .FPUStallD, .ForwardXE, .ForwardYE, .ForwardZE); .XEnD, .YEnD, .ZEnD, .FPUStallD, .ForwardXE, .ForwardYE, .ForwardZE);
// forwarding muxs // forwarding muxs
mux3 #(`FLEN) fxemux (FRD1E, FPUResultW, PreFpResM, ForwardXE, XE); mux3 #(`FLEN) fxemux (FRD1E, FPUResultW, PreFpResM, ForwardXE, XE);