diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index 6adc5ad2d..480556aaa 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -142,8 +142,7 @@ module ifu (
mmu #(.TLB_ENTRIES(`ITLB_ENTRIES), .IMMU(1))
immu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
.PrivilegeModeW, .DisableTranslation(1'b0),
- .PAdr(PCFExt[`PA_BITS-1:0]),
- .VAdr(PCFSpill),
+ .VAdr(PCFExt),
.Size(2'b10),
.PTE(PTE),
.PageTypeWriteVal(PageType),
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index 7442aea70..d5e5b2b35 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -91,7 +91,7 @@ module lsu (
logic [2:0] LSUFunct3M;
logic [6:0] LSUFunct7M;
logic [1:0] LSUAtomicM;
- (* mark_debug = "true" *) logic [`PA_BITS-1:0] PreLSUPAdrM;
+ (* mark_debug = "true" *) logic [`XLEN+1:0] PreLSUPAdrM;
logic [11:0] PreLSUAdrE, LSUAdrE;
logic CPUBusy;
logic DCacheStallM;
@@ -132,7 +132,7 @@ module lsu (
assign {InterlockStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF, IgnoreRequestTLB} = '0;
assign IgnoreRequestTrapM = TrapM; assign CPUBusy = StallW; assign PreLSURWM = MemRWM;
assign LSUAdrE = PreLSUAdrE; assign PreLSUAdrE = IEUAdrE[11:0];
- assign PreLSUPAdrM = IEUAdrExtM[`PA_BITS-1:0];
+ assign PreLSUPAdrM = IEUAdrExtM;
assign LSUFunct3M = Funct3M; assign LSUFunct7M = Funct7M; assign LSUAtomicM = AtomicM;
assign LSUWriteDataM = WriteDataM;
end
@@ -151,8 +151,7 @@ module lsu (
mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
.PrivilegeModeW, .DisableTranslation,
- .PAdr(PreLSUPAdrM),
- .VAdr(IEUAdrM),
+ .VAdr(PreLSUPAdrM),
.Size(LSUFunct3M[1:0]),
.PTE,
.PageTypeWriteVal(PageType),
diff --git a/pipelined/src/lsu/lsuvirtmen.sv b/pipelined/src/lsu/lsuvirtmen.sv
index 83176470e..751c2c928 100644
--- a/pipelined/src/lsu/lsuvirtmen.sv
+++ b/pipelined/src/lsu/lsuvirtmen.sv
@@ -59,7 +59,7 @@ module lsuvirtmem(
output logic [1:0] PreLSURWM,
output logic [1:0] LSUAtomicM,
output logic [11:0] LSUAdrE,
- output logic [`PA_BITS-1:0] PreLSUPAdrM,
+ output logic [`XLEN+1:0] PreLSUPAdrM,
input logic [`XLEN+1:0] IEUAdrExtM, // *** can move internally.
output logic InterlockStall,
@@ -71,13 +71,15 @@ module lsuvirtmem(
logic AnyCPUReqM;
logic [`PA_BITS-1:0] HPTWAdr;
+ logic [`XLEN+1:0] HPTWAdrExt;
logic [1:0] HPTWRW;
logic [2:0] HPTWSize;
logic SelReplayMemE;
logic [11:0] PreLSUAdrE;
logic ITLBMissOrDAFaultF, ITLBMissOrDAFaultNoTrapF;
- logic DTLBMissOrDAFaultM, DTLBMissOrDAFaultNoTrapM;
-
+ logic DTLBMissOrDAFaultM, DTLBMissOrDAFaultNoTrapM;
+ logic SelHPTWAdr;
+
assign ITLBMissOrDAFaultF = ITLBMissF | (`HPTW_WRITES_SUPPORTED & InstrDAPageFaultF);
assign DTLBMissOrDAFaultM = DTLBMissM | (`HPTW_WRITES_SUPPORTED & DataDAPageFaultM);
assign ITLBMissOrDAFaultNoTrapF = ITLBMissOrDAFaultF & ~TrapM;
@@ -94,13 +96,22 @@ module lsuvirtmem(
.DCacheStallM, .HPTWAdr, .HPTWRW, .HPTWSize);
// *** possible future optimization of simplifying page table entry with precomputed misalignment (Ross) low priority
+ // Once the walk is done and it is time to update the DTLB we need to switch back
+ // to the orignal data virtual address.
+ assign SelHPTWAdr = SelHPTW & ~DTLBWriteM;
+
// multiplex the outputs to LSU
+ if(`XLEN+2-`PA_BITS > 0) begin
+ logic [(`XLEN+2-`PA_BITS)-1:0] zeros;
+ assign zeros = '0;
+ assign HPTWAdrExt = {zeros, HPTWAdr};
+ end else assign HPTWAdrExt = HPTWAdr;
mux2 #(2) rwmux(MemRWM, HPTWRW, SelHPTW, PreLSURWM);
mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, LSUFunct3M);
mux2 #(7) funct7mux(Funct7M, 7'b0, SelHPTW, LSUFunct7M);
mux2 #(2) atomicmux(AtomicM, 2'b00, SelHPTW, LSUAtomicM);
mux2 #(12) adremux(IEUAdrE[11:0], HPTWAdr[11:0], SelHPTW, PreLSUAdrE);
- mux2 #(`PA_BITS) lsupadrmux(IEUAdrExtM[`PA_BITS-1:0], HPTWAdr, SelHPTW, PreLSUPAdrM);
+ mux2 #(`XLEN+2) lsupadrmux(IEUAdrExtM, HPTWAdrExt, SelHPTWAdr, PreLSUPAdrM);
if(`HPTW_WRITES_SUPPORTED)
mux2 #(`XLEN) lsuwritedatamux(WriteDataM, PTE, SelHPTW, LSUWriteDataM);
else assign LSUWriteDataM = WriteDataM;
diff --git a/pipelined/src/mmu/mmu.sv b/pipelined/src/mmu/mmu.sv
index 0d53aaccd..ccf49ce48 100644
--- a/pipelined/src/mmu/mmu.sv
+++ b/pipelined/src/mmu/mmu.sv
@@ -49,16 +49,10 @@ module mmu #(parameter TLB_ENTRIES = 8, // number of TLB Entries
// 11 - TLB is accessed for both read and write
input logic DisableTranslation,
- // VAdr goes to the TLB only. Virtual if the TLB is active.
- // PAdr goes to address mux bypassing the TLB. PAdr used when there is no translation.
- // Comes from either the program address (instruction address or load/store address)
- // or from the hardware pagetable walker.
- // PAdr is intended to used as a phsycial address. Discarded by the address mux when translation is
- // performed.
+ // VAdr is the virtual/physical address from IEU or physical address from HPTW.
// PhysicalAddress is selected to be PAdr when no translation or the translated VAdr (TLBPAdr)
// when there is translation.
- input logic [`PA_BITS-1:0] PAdr, // *** consider renaming this.
- input logic [`XLEN-1:0] VAdr,
+ input logic [`XLEN+1:0] VAdr,
input logic [1:0] Size, // 00 = 8 bits, 01 = 16 bits, 10 = 32 bits , 11 = 64 bits
// Controls for writing a new entry to the TLB
@@ -106,7 +100,7 @@ module mmu #(parameter TLB_ENTRIES = 8, // number of TLB Entries
tlb(.clk, .reset,
.SATP_MODE(SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS]),
.SATP_ASID(SATP_REGW[`ASID_BASE+`ASID_BITS-1:`ASID_BASE]),
- .VAdr, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
+ .VAdr(VAdr[`XLEN-1:0]), .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
.PrivilegeModeW, .ReadAccess, .WriteAccess,
.DisableTranslation, .PTE, .PageTypeWriteVal,
.TLBWrite, .TLBFlush, .TLBPAdr, .TLBMiss, .TLBHit,
@@ -122,8 +116,8 @@ module mmu #(parameter TLB_ENTRIES = 8, // number of TLB Entries
// the lower 12 bits are the page offset. These are never changed from the orginal
// non translated address.
//mux2 #(`PA_BITS) addressmux(PAdr, TLBPAdr, Translate, PhysicalAddress);
- mux2 #(`PA_BITS-12) addressmux(PAdr[`PA_BITS-1:12], TLBPAdr[`PA_BITS-1:12], Translate, PhysicalAddress[`PA_BITS-1:12]);
- assign PhysicalAddress[11:0] = PAdr[11:0];
+ mux2 #(`PA_BITS-12) addressmux(VAdr[`PA_BITS-1:12], TLBPAdr[`PA_BITS-1:12], Translate, PhysicalAddress[`PA_BITS-1:12]);
+ assign PhysicalAddress[11:0] = VAdr[11:0];
///////////////////////////////////////////