From fe5f342d2f282c5a307e6bbcb13b3917ed0ee9c3 Mon Sep 17 00:00:00 2001
From: Rose Thompson <rose@rosethompson.net>
Date: Fri, 11 Oct 2024 12:07:26 -0500
Subject: [PATCH] Does not work. But there is a bug hiding the IgnoreRequest
 confusion.

---
 src/lsu/lsu.sv  | 4 ++--
 src/mmu/hptw.sv | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv
index bc8852cf4..a068bf172 100644
--- a/src/lsu/lsu.sv
+++ b/src/lsu/lsu.sv
@@ -342,7 +342,7 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
         .FetchBuffer, .CacheBusRW(CacheBusRWTemp), 
         .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0), .CMOpM(CacheCMOpM));
 
-      assign DCacheStallM = CacheStall & ~IgnoreRequestTLB;
+      assign DCacheStallM = CacheStall;
       assign CacheBusRW = CacheBusRWTemp;
 
       ahbcacheinterface #(.P(P), .BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN),  .LLENPOVERAHBW(LLENPOVERAHBW), .READ_ONLY_CACHE(0)) ahbcacheinterface(
@@ -386,7 +386,7 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
     assign {DCacheStallM, DCacheCommittedM} = '0;
   end
 
-  assign LSUBusStallM = BusStall & ~IgnoreRequestTLB;
+  assign LSUBusStallM = BusStall;
   
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Atomic operations
diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv
index daed5dde5..ee22e3a70 100644
--- a/src/mmu/hptw.sv
+++ b/src/mmu/hptw.sv
@@ -300,7 +300,7 @@ module hptw import cvw::*;  #(parameter cvw_t P) (
       default:                                                        NextWalkerState = IDLE; // Should never be reached
     endcase // case (WalkerState)
 
-  assign IgnoreRequestTLB = (WalkerState == IDLE & TLBMissOrUpdateDA) | (HPTWFaultM); // If hptw request has pmp/a fault suppress bus access.
+  assign IgnoreRequestTLB = (WalkerState == IDLE & TLBMissOrUpdateDA) | (WalkerState != IDLE & HPTWFaultM); // If hptw request has pmp/a fault suppress bus access.
   assign SelHPTW = WalkerState != IDLE;
   assign HPTWStall = (WalkerState != IDLE & WalkerState != FAULT) | (WalkerState == IDLE & TLBMissOrUpdateDA);