diff --git a/pipelined/regression/lint-wally b/pipelined/regression/lint-wally index b51797e66..000b63402 100755 --- a/pipelined/regression/lint-wally +++ b/pipelined/regression/lint-wally @@ -5,8 +5,8 @@ export PATH=$PATH:/usr/local/bin/ verilator=`which verilator` basepath=$(dirname $0)/.. -#for config in rv32e rv64gc rv32gc rv32ic rv32i rv64i rv64fpquad; do -for config in rv64gc; do +for config in rv32e rv64gc rv32gc rv32ic rv32i rv64i rv64fpquad; do +#for config in rv64gc; do echo "$config linting..." if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then echo "Exiting after $config lint due to errors or warnings" diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv index b4c4964d2..80cd4e3ab 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv @@ -42,7 +42,6 @@ module fdivsqrt( input logic XNaNE, YNaNE, input logic FDivStartE, IDivStartE, input logic StallM, - input logic StallE, input logic FlushE, input logic SqrtE, SqrtM, input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B @@ -75,17 +74,17 @@ module fdivsqrt( .clk, .IFDivStartE, .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE), .Sqrt(SqrtE), .Ym(YmE), .XZeroE, .X, .DPreproc, .ForwardedSrcAM, .nE, .nM, .mM, .CalcOTFCSwapE, .OTFCSwapE, .ALTBM, .AZeroM, .BZeroM, .AZeroE, .BZeroE, .As, - .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E); + .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .MDUE, .W64E); fdivsqrtfsm fdivsqrtfsm( .clk, .reset, .FmtE, .XsE, .SqrtE, .nE, - .FDivBusyE, .FDivStartE, .IDivStartE, .IFDivStartE, .FDivDoneE, .StallE, .StallM, .FlushE, /*.DivDone, */ + .FDivBusyE, .FDivStartE, .IDivStartE, .IFDivStartE, .FDivDoneE, .StallM, .FlushE, /*.DivDone, */ .XZeroE, .YZeroE, .AZeroE, .BZeroE, .XNaNE, .YNaNE, .MDUE, .XInfE, .YInfE, .WZeroM, .SpecialCaseM); fdivsqrtiter fdivsqrtiter( .clk, .Firstun, .D, .FirstU, .FirstUM, .FirstC, .MDUE, .SqrtE, // .SqrtM, .X,.DPreproc, .FirstWS(WS), .FirstWC(WC), - .IFDivStartE, .Xe(XeE), .Ye(YeE), .XZeroE, .YZeroE, .CalcOTFCSwapE, .OTFCSwapE, + .IFDivStartE, .CalcOTFCSwapE, .OTFCSwapE, .FDivBusyE); fdivsqrtpostproc fdivsqrtpostproc( .WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun, diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv index 851dc27a5..6a7bbac2e 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv @@ -41,7 +41,6 @@ module fdivsqrtfsm( input logic FDivStartE, IDivStartE, input logic XsE, input logic SqrtE, - input logic StallE, input logic StallM, input logic FlushE, input logic WZeroM, diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv index 75145e55a..b91728eac 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv @@ -34,8 +34,6 @@ module fdivsqrtiter( input logic clk, input logic IFDivStartE, input logic FDivBusyE, - input logic [`NE-1:0] Xe, Ye, - input logic XZeroE, YZeroE, input logic SqrtE, MDUE, // input logic SqrtM, input logic CalcOTFCSwapE, OTFCSwapE, @@ -64,7 +62,6 @@ module fdivsqrtiter( logic [`DIVb+3:0] WSN, WCN; // Q4.b logic [`DIVb+3:0] DBar, D2, DBar2; // Q4.b logic [`DIVb+1:0] NextC; - logic [`DIVb+1:0] CMux; logic [`DIVb:0] UMux, UMMux; logic [`DIVb:0] initU, initUM; /* verilator lint_on UNOPTFLAT */ @@ -94,8 +91,8 @@ module fdivsqrtiter( logic [1:0] initCUpper; assign initCUpper = (SqrtE & ~(MDUE)) ? 2'b11 : (`RADIX == 4) ? 2'b00 : 2'b10; assign initC = {initCUpper, {`DIVb{1'b0}}}; - mux2 #(`DIVb+2) Cmux(C[`DIVCOPIES], initC, IFDivStartE, CMux); - flopen #(`DIVb+2) creg(clk, IFDivStartE|FDivBusyE, CMux, C[0]); + mux2 #(`DIVb+2) Cmux(C[`DIVCOPIES], initC, IFDivStartE, NextC); + flopen #(`DIVb+2) creg(clk, IFDivStartE|FDivBusyE, NextC, C[0]); // Divisior register flopen #(`DIVb) dreg(clk, IFDivStartE, DPreproc, D); diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index 0bd3fae07..902b02760 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -39,7 +39,7 @@ module fdivsqrtpreproc ( input logic Sqrt, input logic XZeroE, input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B - input logic [2:0] Funct3E, Funct3M, + input logic [2:0] Funct3E, input logic MDUE, W64E, output logic [`DIVBLEN:0] nE, nM, mM, output logic CalcOTFCSwapE, OTFCSwapE, ALTBM, As, AZeroM, BZeroM, AZeroE, BZeroE, diff --git a/pipelined/src/fpu/fma/fma.sv b/pipelined/src/fpu/fma/fma.sv index ce42aaa19..c1a69e6fc 100644 --- a/pipelined/src/fpu/fma/fma.sv +++ b/pipelined/src/fpu/fma/fma.sv @@ -36,7 +36,6 @@ module fma( input logic [`NF:0] Xm, Ym, Zm, // input's significands in U(0.NF) format input logic XZero, YZero, ZZero, // is the input zero input logic [2:0] OpCtrl, // 000 = fmadd (X*Y)+Z, 001 = fmsub (X*Y)-Z, 010 = fnmsub -(X*Y)+Z, 011 = fnmadd -(X*Y)-Z, 100 = fmul (X*Y) - input logic [`FMTBITS-1:0] Fmt, // format of the result single double half or quad output logic ZmSticky, // sticky bit that is calculated during alignment output logic [3*`NF+5:0] Sm, // the positive sum's significand output logic InvA, // Was A inverted for effective subtraction (P-A or -P+A) @@ -64,7 +63,7 @@ module fma( // calculate the product's exponent - fmaexpadd expadd(.Fmt, .Xe, .Ye, .XZero, .YZero, .Pe); + fmaexpadd expadd(.Xe, .Ye, .XZero, .YZero, .Pe); // multiplication of the mantissa's fmamult mult(.Xm, .Ym, .Pm); @@ -84,7 +83,7 @@ module fma( // // Addition/LZA // /////////////////////////////////////////////////////////////////////////////// - fmaadd add(.Am, .Pm, .Ze, .Pe, .Ps, .As, .KillProd, .ZmSticky, .AmInv, .PmKilled, .InvA, .Sm, .Se, .Ss); + fmaadd add(.Am, .Pm, .Ze, .Pe, .Ps, .KillProd, .ZmSticky, .AmInv, .PmKilled, .InvA, .Sm, .Se, .Ss); fmalza #(3*`NF+6) lza(.A(AmInv), .Pm({PmKilled, 1'b0, InvA&Ps&ZmSticky&KillProd}), .Cin(InvA & ~(ZmSticky & ~KillProd)), .sub(InvA), .SCnt); endmodule diff --git a/pipelined/src/fpu/fma/fmaadd.sv b/pipelined/src/fpu/fma/fmaadd.sv index 16cf6b05e..c040c241f 100644 --- a/pipelined/src/fpu/fma/fmaadd.sv +++ b/pipelined/src/fpu/fma/fmaadd.sv @@ -33,7 +33,7 @@ module fmaadd( input logic [3*`NF+5:0] Am, // aligned addend's mantissa for addition in U(NF+5.2NF+1) input logic [2*`NF+1:0] Pm, // the product's mantissa - input logic Ps, As,// the product sign and the alligend addeded's sign (Modified Z sign for other opperations) + input logic Ps, // the product sign and the alligend addeded's sign (Modified Z sign for other opperations) input logic InvA, // invert the aligned addend input logic KillProd, // should the product be set to 0 input logic ZmSticky, diff --git a/pipelined/src/fpu/fma/fmaexpadd.sv b/pipelined/src/fpu/fma/fmaexpadd.sv index 33919d7a3..9f338891e 100644 --- a/pipelined/src/fpu/fma/fmaexpadd.sv +++ b/pipelined/src/fpu/fma/fmaexpadd.sv @@ -31,7 +31,6 @@ `include "wally-config.vh" module fmaexpadd( - input logic [`FMTBITS-1:0] Fmt, // format of the output: single double half quad input logic [`NE-1:0] Xe, Ye, // input's exponents input logic XZero, YZero, // are the inputs zero output logic [`NE+1:0] Pe // product's exponent B^(1023)NE+2 diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index afa645cde..041fd5ff0 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -252,7 +252,7 @@ module fpu ( .Xe(XeE), .Ye(YeE), .Ze(ZeE), .Xm(XmE), .Ym(YmE), .Zm(ZmE), .XZero(XZeroE), .YZero(YZeroE), .ZZero(ZZeroE), - .OpCtrl(OpCtrlE), .Fmt(FmtE), + .OpCtrl(OpCtrlE), .As(AsE), .Ps(PsE), .Ss(SsE), .Se(SeE), .Sm(SmE), .InvA(InvAE), .SCnt(SCntE), @@ -265,7 +265,7 @@ module fpu ( fdivsqrt fdivsqrt(.clk, .reset, .FmtE, .XmE, .YmE, .XeE, .YeE, .SqrtE(OpCtrlE[0]), .SqrtM(OpCtrlM[0]), .XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .FDivStartE, .IDivStartE, .XsE, .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E, - .StallE, .StallM, .FlushE, .DivSM, .FDivBusyE, .IFDivStartE, .FDivDoneE, .QeM, + .StallM, .FlushE, .DivSM, .FDivBusyE, .IFDivStartE, .FDivDoneE, .QeM, .QmM, .FPIntDivResultM /*, .DivDone(DivDoneM) */); // @@ -372,7 +372,7 @@ module fpu ( assign FpLoadStoreM = FResSelM[1]; - postprocess postprocess(.Xs(XsM), .Ys(YsM), .Ze(ZeM), .Xm(XmM), .Ym(YmM), .Zm(ZmM), .Frm(FrmM), .Fmt(FmtM), + postprocess postprocess(.Xs(XsM), .Ys(YsM), .Xm(XmM), .Ym(YmM), .Zm(ZmM), .Frm(FrmM), .Fmt(FmtM), .FmaZmS(ZmStickyM), .XZero(XZeroM), .YZero(YZeroM), .ZZero(ZZeroM), .XInf(XInfM), .YInf(YInfM), .DivQm(QmM), .FmaSs(SsM), .ZInf(ZInfM), .XNaN(XNaNM), .YNaN(YNaNM), .ZNaN(ZNaNM), .XSNaN(XSNaNM), .YSNaN(YSNaNM), .ZSNaN(ZSNaNM), .FmaSm(SmM), .DivQe(QeM), /*.DivDone(DivDoneM), */ .ZDenorm(ZDenormM), .FmaAs(AsM), .FmaPs(PsM), .OpCtrl(OpCtrlM), .FmaSCnt(SCntM), .FmaSe(SeM), diff --git a/pipelined/src/fpu/postproc/divshiftcalc.sv b/pipelined/src/fpu/postproc/divshiftcalc.sv index 58fd9b9b6..0f0e2d368 100644 --- a/pipelined/src/fpu/postproc/divshiftcalc.sv +++ b/pipelined/src/fpu/postproc/divshiftcalc.sv @@ -32,7 +32,6 @@ module divshiftcalc( input logic [`DIVb:0] DivQm, - input logic [`FMTBITS-1:0] Fmt, input logic Sqrt, input logic [`NE+1:0] DivQe, output logic [`LOGNORMSHIFTSZ-1:0] DivShiftAmt, diff --git a/pipelined/src/fpu/postproc/fmashiftcalc.sv b/pipelined/src/fpu/postproc/fmashiftcalc.sv index ce9ff79b1..1e8012784 100644 --- a/pipelined/src/fpu/postproc/fmashiftcalc.sv +++ b/pipelined/src/fpu/postproc/fmashiftcalc.sv @@ -31,7 +31,6 @@ module fmashiftcalc( input logic [3*`NF+5:0] FmaSm, // the positive sum - input logic [`NE-1:0] Ze, // exponent of Z input logic [$clog2(3*`NF+7)-1:0] FmaSCnt, // normalization shift count input logic [`FMTBITS-1:0] Fmt, // precision 1 = double 0 = single input logic [`NE+1:0] FmaSe, diff --git a/pipelined/src/fpu/postproc/postprocess.sv b/pipelined/src/fpu/postproc/postprocess.sv index 0880d33e2..368f3ef77 100644 --- a/pipelined/src/fpu/postproc/postprocess.sv +++ b/pipelined/src/fpu/postproc/postprocess.sv @@ -33,7 +33,6 @@ module postprocess ( // general signals input logic Xs, Ys, // input signs - input logic [`NE-1:0] Ze, // input exponents input logic [`NF:0] Xm, Ym, Zm, // input mantissas input logic [2:0] Frm, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude input logic [`FMTBITS-1:0] Fmt, // precision 1 = double 0 = single @@ -146,9 +145,9 @@ module postprocess ( cvtshiftcalc cvtshiftcalc(.ToInt, .CvtCe, .CvtResDenormUf, .Xm, .CvtLzcIn, .XZero, .IntToFp, .OutFmt, .CvtResUf, .CvtShiftIn); - fmashiftcalc fmashiftcalc(.FmaSm, .Ze, .FmaSCnt, .Fmt, .NormSumExp, .FmaSe, + fmashiftcalc fmashiftcalc(.FmaSm, .FmaSCnt, .Fmt, .NormSumExp, .FmaSe, .FmaSZero, .FmaPreResultDenorm, .FmaShiftAmt, .FmaShiftIn); - divshiftcalc divshiftcalc(.Fmt, .Sqrt, .DivQe, .DivQm, .DivResDenorm, .DivDenormShiftPos, .DivShiftAmt, .DivShiftIn); + divshiftcalc divshiftcalc(.Sqrt, .DivQe, .DivQm, .DivResDenorm, .DivDenormShiftPos, .DivShiftAmt, .DivShiftIn); always_comb case(PostProcSel)