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fix testbench timing bug where interrupt forcing didn't happen soon enough because it was waiting on StallM

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bbracker 2022-04-14 09:23:21 -07:00
parent eb21e34000
commit fe53dd1683
1 changed files with 4 additions and 1 deletions
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5
pipelined/testbench/testbench-linux.sv
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@ -729,8 +729,11 @@ module testbench;
// New IP spoofing // New IP spoofing
logic globalIntsBecomeEnabled; logic globalIntsBecomeEnabled;
assign globalIntsBecomeEnabled = (`CSR_BASE.csrm.WriteMSTATUSM || `CSR_BASE.csrs.WriteSSTATUSM) && (|(`CSR_BASE.CSRWriteValM & (~`CSR_BASE.csrm.MSTATUS_REGW) & 32'h22)); assign globalIntsBecomeEnabled = (`CSR_BASE.csrm.WriteMSTATUSM || `CSR_BASE.csrs.WriteSSTATUSM) && (|(`CSR_BASE.CSRWriteValM & (~`CSR_BASE.csrm.MSTATUS_REGW) & 32'h22));
logic checkInterruptM;
assign checkInterruptM = dut.core.ieu.InstrValidM & ~dut.core.priv.priv.trap.InstrPageFaultM & ~dut.core.priv.priv.trap.InterruptM;
always @(negedge clk) begin always @(negedge clk) begin
if(checkInstrM) begin if(checkInterruptM) begin
if((interruptInstrCount+1) == AttemptedInstructionCount) begin if((interruptInstrCount+1) == AttemptedInstructionCount) begin
if(!NO_IE_MTIME_CHECKPOINT) begin if(!NO_IE_MTIME_CHECKPOINT) begin
case (interruptCauseVal) case (interruptCauseVal)