From fe3147806d74f9ce7b6185f8920e318f7c3d158f Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 25 Aug 2022 03:39:57 -0700 Subject: [PATCH] removed simpleram and modified dtim to use bram1p1rw --- pipelined/src/generic/flop/simpleram.sv | 48 ------------------- pipelined/src/generic/mem/bram1p1rw.sv | 4 +- pipelined/src/generic/mem/bram1p1rw_64x128.sv | 2 +- pipelined/src/lsu/dtim.sv | 20 +++++--- pipelined/src/lsu/lsu.sv | 2 - pipelined/testbench/testbench-linux.sv | 3 +- 6 files changed, 18 insertions(+), 61 deletions(-) delete mode 100644 pipelined/src/generic/flop/simpleram.sv diff --git a/pipelined/src/generic/flop/simpleram.sv b/pipelined/src/generic/flop/simpleram.sv deleted file mode 100644 index 08c7d113b..000000000 --- a/pipelined/src/generic/flop/simpleram.sv +++ /dev/null @@ -1,48 +0,0 @@ -/////////////////////////////////////////// -// simpleram.sv -// -// Written: David_Harris@hmc.edu 9 January 2021 -// Modified: -// -// Purpose: On-chip SIMPLERAM, external to core -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// MIT LICENSE -// Permission is hereby granted, free of charge, to any person obtaining a copy of this -// software and associated documentation files (the "Software"), to deal in the Software -// without restriction, including without limitation the rights to use, copy, modify, merge, -// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons -// to whom the Software is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or -// substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE -// OR OTHER DEALINGS IN THE SOFTWARE. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module simpleram #(parameter BASE=0, RANGE = 65535) ( - input logic clk, - input logic [31:0] a, - input logic we, - input logic [`LLEN/8-1:0] ByteMask, - input logic [`LLEN-1:0] wd, - output logic [`LLEN-1:0] rd -); - - localparam ADDR_WDITH = $clog2(RANGE/8); - localparam OFFSET = $clog2(`LLEN/8); - - bram1p1rw #(`LLEN/8, 8, ADDR_WDITH) - memory(.clk, .we, .bwe(ByteMask), .addr(a[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(rd), .din(wd)); -endmodule - diff --git a/pipelined/src/generic/mem/bram1p1rw.sv b/pipelined/src/generic/mem/bram1p1rw.sv index 51fe54214..31ed99a74 100644 --- a/pipelined/src/generic/mem/bram1p1rw.sv +++ b/pipelined/src/generic/mem/bram1p1rw.sv @@ -5,8 +5,8 @@ // March 29, 2022 // Modified: Based on UG901 vivado documentation. // -// Purpose: On-chip SIMPLERAM, external to core -// +/// Purpose: On-chip RAM array +// // A component of the Wally configurable RISC-V project. // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University diff --git a/pipelined/src/generic/mem/bram1p1rw_64x128.sv b/pipelined/src/generic/mem/bram1p1rw_64x128.sv index 48d28d719..eaa5c7f7f 100644 --- a/pipelined/src/generic/mem/bram1p1rw_64x128.sv +++ b/pipelined/src/generic/mem/bram1p1rw_64x128.sv @@ -5,7 +5,7 @@ // March 29, 2022 // Modified: Based on UG901 vivado documentation. // -// Purpose: On-chip SIMPLERAM, external to core +// Purpose: On-chip RAM array // // A component of the Wally configurable RISC-V project. // diff --git a/pipelined/src/lsu/dtim.sv b/pipelined/src/lsu/dtim.sv index e5dc27cf6..7c2e066c9 100644 --- a/pipelined/src/lsu/dtim.sv +++ b/pipelined/src/lsu/dtim.sv @@ -47,13 +47,19 @@ module dtim( output logic DCacheStallM, output logic DCacheCommittedM, output logic DCacheMiss, - output logic DCacheAccess); - - simpleram #(.BASE(`UNCORE_RAM_BASE), .RANGE(`UNCORE_RAM_RANGE)) ram ( - .clk, .ByteMask(ByteMaskM), - .a(CPUBusy | LSURWM[0] | reset ? IEUAdrM[31:0] : IEUAdrE[31:0]), // move mux out; this shouldn't be needed when stails are handled differently *** - .we(LSURWM[0] & Cacheable & ~TrapM), // have to ignore write if Trap. - .wd(WriteDataM), .rd(ReadDataWordM)); + output logic DCacheAccess +); + + logic we; + +// localparam ADDR_WDITH = $clog2(`TIM_RAM_RANGE/8); // *** replace with tihs when defined + localparam ADDR_WDITH = $clog2(`UNCORE_RAM_RANGE/8); // *** this is the wrong size + localparam OFFSET = $clog2(`LLEN/8); + + assign we = LSURWM[0] & Cacheable & ~TrapM; // have to ignore write if Trap. + + bram1p1rw #(`LLEN/8, 8, ADDR_WDITH) + ram(.clk, .we, .bwe(ByteMaskM), .addr(IEUAdrE[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM)); // since we have a local memory the bus connections are all disabled. // There are no peripherals supported. diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index b2b5dac09..819a0c70c 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -200,8 +200,6 @@ module lsu ( // use the same UNCORE_RAM_BASE addresss for both the DTIM and any RAM in the Uncore. if (`DMEM) begin : dtim - // *** directly instantiate RAM or ROM here. Instantiate SRAM1P1RW. - // Merge SimpleRAM and SRAM1p1rw into one that is good for synthesis and RAM libraries and flops dtim dtim(.clk, .reset, .CPUBusy, .LSURWM, .IEUAdrM, .IEUAdrE, .TrapM, .WriteDataM(LSUWriteDataM), //*** fix the dtim FinalWriteData .ReadDataWordM(ReadDataWordM[`XLEN-1:0]), .BusStall, .LSUBusWrite,.LSUBusRead, .BusCommittedM, .DCacheStallM, .DCacheCommittedM, .ByteMaskM(ByteMaskM[`XLEN/8-1:0]), .Cacheable(CacheableM), diff --git a/pipelined/testbench/testbench-linux.sv b/pipelined/testbench/testbench-linux.sv index a93b4b990..cf6a6d394 100644 --- a/pipelined/testbench/testbench-linux.sv +++ b/pipelined/testbench/testbench-linux.sv @@ -246,6 +246,7 @@ module testbench; logic HSELEXT; logic [31:0] HADDR; logic [`AHBW-1:0] HWDATA; + logic [`XLEN/8-1:0] HWSTRB; logic HWRITE; logic [2:0] HSIZE; logic [2:0] HBURST; @@ -270,7 +271,7 @@ module testbench; // Wally wallypipelinedsoc dut(.clk, .reset, .reset_ext, .HRDATAEXT, .HREADYEXT, .HREADY, .HSELEXT, .HRESPEXT, .HCLK, - .HRESETn, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT, + .HRESETn, .HADDR, .HWDATA, .HWRITE, .HWSTRB, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .TIMECLK('0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout,