diff --git a/README.md b/README.md
index 559c3e0ee..420ea87a1 100644
--- a/README.md
+++ b/README.md
@@ -14,6 +14,8 @@ cd ../addins
 git clone https://github.com/riscv-non-isa/riscv-arch-test
 git clone https://github.com/riscv-software-src/riscv-isa-sim
 cd riscv-isa-sim
+cp -r arch_test_target/spike/device/rv32i_m/I arch_test_target/spike/device/rv32i_m/F
+<edit arch_test_target/spike/device/rv32i_m/F/Makefile.include line 35 and change --isa=rv32i to --isa=rv32if>
 mkdir build
 cd build
 set RISCV=/cad/riscv/gcc/bin   (or whatever your path is)
diff --git a/wally-pipelined/regression/regression-wally.py b/wally-pipelined/regression/regression-wally.py
index ec06956b3..79532c5c8 100755
--- a/wally-pipelined/regression/regression-wally.py
+++ b/wally-pipelined/regression/regression-wally.py
@@ -48,6 +48,7 @@ for test in tests64:
         cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv64g "+test+"\n!",
         grepstr="All tests ran without failures")
   configs.append(tc)
+#tests32 = ["arch32i", "arch32priv", "arch32c",  "arch32m", "arch32f", "imperas32i", "imperas32p", "imperas32mmu", "imperas32f", "imperas32m", "imperas32a",  "imperas32c"]
 tests32 = ["arch32i", "arch32priv", "arch32c",  "arch32m", "imperas32i", "imperas32p", "imperas32mmu", "imperas32f", "imperas32m", "imperas32a",  "imperas32c"]
 for test in tests32:
   tc = TestCase(
diff --git a/wally-pipelined/regression/sim-wally b/wally-pipelined/regression/sim-wally
index 9985a0086..1479d0079 100755
--- a/wally-pipelined/regression/sim-wally
+++ b/wally-pipelined/regression/sim-wally
@@ -1,2 +1,2 @@
-vsim -do "do wally-pipelined.do rv32g arch32m"
+vsim -do "do wally-pipelined.do rv32g arch32f"
 
diff --git a/wally-pipelined/regression/sim-wally-batch b/wally-pipelined/regression/sim-wally-batch
index 06a66a106..4b627b768 100755
--- a/wally-pipelined/regression/sim-wally-batch
+++ b/wally-pipelined/regression/sim-wally-batch
@@ -1,3 +1,3 @@
 vsim -c <<!
-do wally-pipelined-batch.do rv64g arch64m
+do wally-pipelined-batch.do rv32g arch32f
 !
diff --git a/wally-pipelined/regression/wave-dos/peripheral-waves.do b/wally-pipelined/regression/wave-dos/peripheral-waves.do
index 6eec4995d..f5382c3bc 100644
--- a/wally-pipelined/regression/wave-dos/peripheral-waves.do
+++ b/wally-pipelined/regression/wave-dos/peripheral-waves.do
@@ -53,7 +53,7 @@ add wave -hex /testbench/dut/hart/lsu/dcache/ReadDataM
 add wave -divider
 add wave -hex /testbench/PCW
 #add wave -hex /testbench/InstrW
-add wave -hex /testbench/dut/hart/ieu/c/InstrValidW
+#add wave -hex /testbench/dut/hart/ieu/c/InstrValidW
 #add wave /testbench/InstrWName
 add wave -hex /testbench/dut/hart/ReadDataW
 add wave -hex /testbench/dut/hart/ieu/dp/ResultW
diff --git a/wally-pipelined/src/cache/cachereplacementpolicy.sv b/wally-pipelined/src/cache/cachereplacementpolicy.sv
index d2739a7c3..e02c36753 100644
--- a/wally-pipelined/src/cache/cachereplacementpolicy.sv
+++ b/wally-pipelined/src/cache/cachereplacementpolicy.sv
@@ -49,7 +49,7 @@ module cachereplacementpolicy
   logic 					LRUWriteEnD;
   
   /* verilator lint_off BLKLOOPINIT */
-  always_ff @(posedge clk, posedge reset) begin
+  always_ff @(posedge clk) begin
     if (reset) begin
       RAdrD <= '0;
       MemPAdrMD <= '0;
diff --git a/wally-pipelined/src/cache/cacheway.sv b/wally-pipelined/src/cache/cacheway.sv
index bb760bbab..6f9c08554 100644
--- a/wally-pipelined/src/cache/cacheway.sv
+++ b/wally-pipelined/src/cache/cacheway.sv
@@ -111,7 +111,7 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
   assign VictimTagWay = SelFlush ? FlushThisWay : VicDirtyWay;
     
   
-  always_ff @(posedge clk, posedge reset) begin
+  always_ff @(posedge clk) begin
     if (reset) 
   	ValidBits <= {NUMLINES{1'b0}};
     else if (InvalidateAll) 
@@ -134,14 +134,14 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
 
   generate
     if(DIRTY_BITS) begin
-      always_ff @(posedge clk, posedge reset) begin
+      always_ff @(posedge clk) begin
 	if (reset) 
   	  DirtyBits <= {NUMLINES{1'b0}};
 	else if (SetDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[WAdrD] <= 1'b1;
 	else if (ClearDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[WAdrD] <= 1'b0;
       end
 
-      always_ff @(posedge clk, posedge reset) begin
+      always_ff @(posedge clk) begin
 	SetDirtyD <= SetDirty;
 	ClearDirtyD <= ClearDirty;
       end
diff --git a/wally-pipelined/src/cache/dcachefsm.sv b/wally-pipelined/src/cache/dcachefsm.sv
index 4fba55bd6..59f90462f 100644
--- a/wally-pipelined/src/cache/dcachefsm.sv
+++ b/wally-pipelined/src/cache/dcachefsm.sv
@@ -144,7 +144,7 @@ module dcachefsm
   assign CntEn = PreCntEn & AHBAck;
 
 
-  always_ff @(posedge clk, posedge reset)
+  always_ff @(posedge clk)
     if (reset)    CurrState <= #1 STATE_READY;
     else CurrState <= #1 NextState;  
   
diff --git a/wally-pipelined/src/cache/icachefsm.sv b/wally-pipelined/src/cache/icachefsm.sv
index 82590747d..2461e0dd4 100644
--- a/wally-pipelined/src/cache/icachefsm.sv
+++ b/wally-pipelined/src/cache/icachefsm.sv
@@ -116,7 +116,7 @@ module icachefsm
   logic 		       PreCntEn;
 
   // the FSM is always runing, do not stall.
-  always_ff @(posedge clk, posedge reset)
+  always_ff @(posedge clk)
     if (reset)    CurrState <= #1 STATE_READY;
     else CurrState <= #1 NextState;
 
diff --git a/wally-pipelined/src/fpu/fpu.sv b/wally-pipelined/src/fpu/fpu.sv
index 6ce894be4..91af05095 100755
--- a/wally-pipelined/src/fpu/fpu.sv
+++ b/wally-pipelined/src/fpu/fpu.sv
@@ -41,7 +41,7 @@ module fpu (
   output logic [`XLEN-1:0] FIntResM, // data to be written to integer register
   output logic 		   FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage)
   output logic 		   IllegalFPUInstrD, // Is the instruction an illegal fpu instruction
-  output logic [4:0] 	   SetFflagsM        // FMA flags (to privileged unit)
+  output logic [4:0] 	   SetFflagsM        // FPU flags (to privileged unit)
   );
 
   //*** make everything FLEN at some point
@@ -267,7 +267,7 @@ module fpu (
      // BEGIN MEMORY STAGE
      
      // FPU flag selection - to privileged
-     mux4  #(5)  FPUFlgMux (5'b0, FMAFlgM, FDivFlgM, FFlgM, FResultSelW, SetFflagsM);
+     mux4  #(5)  FPUFlgMux (5'b0, FMAFlgM, FDivFlgM, FFlgM, FResultSelM, SetFflagsM);
   
      // M/W pipe registers
      flopenrc #(64) MWRegFma(clk, reset, FlushW, ~StallW, FMAResM, FMAResW); 
diff --git a/wally-pipelined/src/ifu/BTBPredictor.sv b/wally-pipelined/src/ifu/BTBPredictor.sv
index 07a39c162..ad94b6ff6 100644
--- a/wally-pipelined/src/ifu/BTBPredictor.sv
+++ b/wally-pipelined/src/ifu/BTBPredictor.sv
@@ -31,25 +31,25 @@
 module BTBPredictor
   #(parameter int Depth = 10
     )
-  (input  logic clk,
-   input logic 		    reset,
-   input logic 		    StallF, StallE,
+  (input  logic             clk,
+   input logic              reset,
+   input logic              StallF, StallE,
    input logic [`XLEN-1:0]  LookUpPC,
    output logic [`XLEN-1:0] TargetPC,
-   output logic [4:0] 	    InstrClass,
-   output logic 	    Valid,
+   output logic [4:0]       InstrClass,
+   output logic             Valid,
    // update
-   input logic 		    UpdateEN,
+   input logic              UpdateEN,
    input logic [`XLEN-1:0]  UpdatePC,
    input logic [`XLEN-1:0]  UpdateTarget,
-   input logic [4:0] 	    UpdateInstrClass,
-   input logic 		    UpdateInvalid
+   input logic [4:0]        UpdateInstrClass,
+   input logic              UpdateInvalid
    );
 
   localparam TotalDepth = 2 ** Depth;
   logic [TotalDepth-1:0]    ValidBits;
-  logic [Depth-1:0] 	    LookUpPCIndex, UpdatePCIndex, LookUpPCIndexQ, UpdatePCIndexQ;
-  logic 		    UpdateENQ;
+  logic [Depth-1:0]         LookUpPCIndex, UpdatePCIndex, LookUpPCIndexQ, UpdatePCIndexQ;
+  logic                     UpdateENQ;
   
 
   // hashing function for indexing the PC
@@ -61,10 +61,10 @@ module BTBPredictor
   
 
   flopenr #(Depth) UpdatePCIndexReg(.clk(clk),
-				    .reset(reset),
-				    .en(~StallE),
-				    .d(UpdatePCIndex),
-				    .q(UpdatePCIndexQ));
+        .reset(reset),
+        .en(~StallE),
+        .d(UpdatePCIndex),
+        .q(UpdatePCIndexQ));
   
   // The valid bit must be resetable.
   always_ff @ (posedge clk) begin
@@ -79,17 +79,17 @@ module BTBPredictor
 
 
   flopenr #(1) UpdateENReg(.clk(clk),
-			  .reset(reset),
-			  .en(~StallF),
-			  .d(UpdateEN),
-			  .q(UpdateENQ));
+     .reset(reset),
+     .en(~StallF),
+     .d(UpdateEN),
+     .q(UpdateENQ));
 
 
   flopenr #(Depth) LookupPCIndexReg(.clk(clk),
-				    .reset(reset),
-				    .en(~StallF),
-				    .d(LookUpPCIndex),
-				    .q(LookUpPCIndexQ));
+        .reset(reset),
+        .en(~StallF),
+        .d(LookUpPCIndex),
+        .q(LookUpPCIndexQ));
 
 
 
@@ -98,14 +98,14 @@ module BTBPredictor
   // *** need to add forwarding.
 
   SRAM2P1R1W #(Depth, `XLEN+5) memory(.clk(clk),
-				      .reset(reset),
-				      .RA1(LookUpPCIndex),
-				      .RD1({{InstrClass, TargetPC}}),
-				      .REN1(~StallF),
-				      .WA1(UpdatePCIndex),
-				      .WD1({UpdateInstrClass, UpdateTarget}),
-				      .WEN1(UpdateEN),
-				      .BitWEN1({5'h1F, {`XLEN{1'b1}}})); // *** definitely not right.
+          .reset(reset),
+          .RA1(LookUpPCIndex),
+          .RD1({{InstrClass, TargetPC}}),
+          .REN1(~StallF),
+          .WA1(UpdatePCIndex),
+          .WD1({UpdateInstrClass, UpdateTarget}),
+          .WEN1(UpdateEN),
+          .BitWEN1({5'h1F, {`XLEN{1'b1}}})); // *** definitely not right.
 
 
 endmodule
diff --git a/wally-pipelined/src/ifu/CodeAligner.py b/wally-pipelined/src/ifu/CodeAligner.py
new file mode 100644
index 000000000..59f9de4e8
--- /dev/null
+++ b/wally-pipelined/src/ifu/CodeAligner.py
@@ -0,0 +1,98 @@
+import os
+
+# Kevin Wan kewan@hmc.edu 10/27/2021
+def read_input(filename):  #1
+    """Takes in a string filename and outputs the parsed verilog code by line into a list
+    such that each element of the list is one line of verilog code as a string."""
+    lineOfCode = []
+    input_file = open(filename, 'r')
+    for line in input_file:
+        lineOfCode.append(line)
+    return lineOfCode
+###################################################################################
+def ID_start(GiantString):#2
+    """takes in the list of sv file lines, outputs the location that variable names should start"""
+    VarLoc = 0 
+    VarLineNum = None
+    for lines in GiantString:
+        if ' logic ' in lines and (lines.find("//") == -1 or lines.find("//") > lines.find(' logic ')): # // logic does not proceed. logic proceeds. logic // proceeds. 
+            if "[" in lines and "]" in lines:# need to account for these space
+                NowLoc = lines.find(']') + 3# column number in sv code when 1st char of the var name should appear. 
+                if NowLoc>VarLoc: 
+                    VarLoc = NowLoc
+                    VarLineNum = GiantString.index(lines) # Update this number if new record is made. 
+            else:   
+                NowLoc = lines.find('logic') + 7 # same as before.
+                if NowLoc>VarLoc: 
+                    VarLoc = NowLoc
+                    VarLineNum = GiantString.index(lines)
+    #print("Furthest variable appears on line", VarLineNum + 1,VarLoc)   # Disable this line after debugging. 
+    return VarLoc
+##################################################################################
+def modified_logNew(GS,SOV): #3
+    Ind = SOV - 1 # SOV is for human readability, Ind is the character's index in computer, since computers count from 0's we need to correct it. 
+    Out = []
+    for l in GS:
+        lines = l.replace('\t',' ')
+
+        if ' logic ' in lines and (lines.find("//") == -1 or lines.find("//") > lines.find(' logic ')): # // logic does not proceed. logic proceeds. logic // proceeds. 
+            if "[" in lines and "]" in lines: # the line is an extended declaration. 
+                EditLoc = lines.find("]") # Re-finds the string index number of ]. 
+                VarLoc = FindCharRel(lines[EditLoc+1::]) + EditLoc + 1  # Checks where variable declaration currently is at. 
+                #print(VarLoc,lines[VarLoc])# VERIFIED
+                NewLine = Mod_Space_at(lines,VarLoc,VarLoc-Ind) 
+                Out.append(NewLine)# Verified0957 10272021
+            else:
+                EditLoc1 = lines.find('c') # Hopefully sees the c in 'logic'
+
+                VarLoc1 = FindCharRel(lines[EditLoc1+1::]) + EditLoc1 + 1
+                NewLine1 = Mod_Space_at(lines,VarLoc1,VarLoc1-Ind)
+
+                Out.append(NewLine1)# Verified 1005 10272021
+        else:
+            Out.append(lines)
+    return Out   
+################################################################################
+def write_to_output(filename,GiantString,OW=True,Lines_editted=None):   #4
+ """Filename is preferrably passed from the early function calls"""
+ """GiantString has all the corrected features in the code, each line is a good verilog code line"""
+ newname = filename
+ if not OW or OW =='f':   #which means no overwrite (create a new file)
+  Decomposed=filename.split('.')
+  newname = Decomposed[0] + "_AL." + Decomposed[1] # AL for aligned. 
+  
+ OutFile = open(newname,'w') # This step should create a new file. 
+ OutFile.writelines(GiantString)
+ OutFile.close()
+ print("Success! " + newname + " Now contains an aligned file!")
+ return newname
+#################################################################################
+
+def FindCharRel(Ln):
+    #returns the computer location of a character's first occurence
+    for num in range(len(Ln)):
+        if Ln[num] != " ":
+            return num 
+
+
+def Mod_Space_at(Ln,loc,diff):
+    #loc is the varLoc from mln, diff is varLoc - Ind
+    if diff > 0: # to delete
+        NewString = Ln[:(loc-diff)] + Ln[loc:]
+        
+    if diff < 0: # to add
+        NewString = Ln[:loc] + (-diff)*" " + Ln[loc:]
+    if diff == 0:
+        NewString = Ln
+    
+    return NewString
+
+def main_filehandler(overwrite=False):
+    for filename in os.listdir():
+        if ".py" not in filename:
+            GiantString = read_input(filename)
+            SOV = ID_start(GiantString)
+            ModifiedGS = modified_logNew(GiantString,SOV)
+            Newname = write_to_output(filename,ModifiedGS,overwrite)
+ 
+main_filehandler(True)
\ No newline at end of file
diff --git a/wally-pipelined/src/ifu/RAsPredictor.sv b/wally-pipelined/src/ifu/RAsPredictor.sv
index bde30be54..31f4568d0 100644
--- a/wally-pipelined/src/ifu/RAsPredictor.sv
+++ b/wally-pipelined/src/ifu/RAsPredictor.sv
@@ -30,21 +30,21 @@
 module RASPredictor
   #(parameter int StackSize = 16
     )
-  (input logic clk,
-   input logic 		    reset,
-   input logic 		    pop,
+  (input logic              clk,
+   input logic              reset,
+   input logic              pop,
    output logic [`XLEN-1:0] popPC,
-   input logic 		    push,
-   input logic 		    incr,
+   input logic              push,
+   input logic              incr,
    input logic [`XLEN-1:0]  pushPC
    );
 
-  logic 		    CounterEn;
+  logic                     CounterEn;
   localparam Depth = $clog2(StackSize);
 
-  logic [Depth-1:0] 	    PtrD, PtrQ, PtrP1, PtrM1;
-  logic [StackSize-1:0] [`XLEN-1:0] memory;
-  integer 			    index;
+  logic [Depth-1:0]         PtrD, PtrQ, PtrP1, PtrM1;
+  logic [StackSize-1:0]     [`XLEN-1:0] memory;
+  integer        index;
   
   assign CounterEn = pop | push | incr;
 
@@ -56,16 +56,16 @@ module RASPredictor
   // *** what happens if jal is executing and there is a return being flushed in Decode?
 
   flopenr #(Depth) PTR(.clk(clk),
-			   .reset(reset),
-			   .en(CounterEn),
-			   .d(PtrD),
-			   .q(PtrQ));
+      .reset(reset),
+      .en(CounterEn),
+      .d(PtrD),
+      .q(PtrQ));
 
   // RAS must be reset. 
-  always_ff @ (posedge clk, posedge reset) begin
+  always_ff @ (posedge clk) begin
     if(reset) begin
       for(index=0; index<StackSize; index++)
-	memory[index] <= {`XLEN{1'b0}};
+ memory[index] <= {`XLEN{1'b0}};
     end else if(push) begin
       memory[PtrP1] <= #1 pushPC;
     end
diff --git a/wally-pipelined/src/ifu/SRAM2P1R1W.sv b/wally-pipelined/src/ifu/SRAM2P1R1W.sv
index 8426ef43b..3a9cf0054 100644
--- a/wally-pipelined/src/ifu/SRAM2P1R1W.sv
+++ b/wally-pipelined/src/ifu/SRAM2P1R1W.sv
@@ -40,68 +40,68 @@ module SRAM2P1R1W
     parameter int WIDTH = 2
     )
 
-  (input logic clk,
+  (input logic              clk,
    // *** have to remove reset eventually
-   input logic 		    reset,
+   input logic              reset,
   
    // port 1 is read only
    input logic [DEPTH-1:0]  RA1,
    output logic [WIDTH-1:0] RD1,
-   input logic 		    REN1,
+   input logic              REN1,
   
    // port 2 is write only
    input logic [DEPTH-1:0]  WA1,
    input logic [WIDTH-1:0]  WD1,
-   input logic 		    WEN1,
+   input logic              WEN1,
    input logic [WIDTH-1:0]  BitWEN1
    );
   
 
-  logic [DEPTH-1:0] 	    RA1Q, WA1Q;
-  logic 		    WEN1Q;
-  logic [WIDTH-1:0] 	    WD1Q;
+  logic [DEPTH-1:0]         RA1Q, WA1Q;
+  logic                     WEN1Q;
+  logic [WIDTH-1:0]         WD1Q;
 
-  logic [WIDTH-1:0] 	    mem[2**DEPTH-1:0];
+  logic [WIDTH-1:0]         mem[2**DEPTH-1:0];
 
   
   // SRAMs address busses are always registered first.
 
   flopenr #(DEPTH) RA1Reg(.clk(clk),
-			  .reset(reset),
-			  .en(REN1),
-			  .d(RA1),
-			  .q(RA1Q));
+     .reset(reset),
+     .en(REN1),
+     .d(RA1),
+     .q(RA1Q));
   
 
   flopenr #(DEPTH) WA1Reg(.clk(clk),
-			  .reset(reset),
-			  .en(REN1),
-			  .d(WA1),
-			  .q(WA1Q));
+     .reset(reset),
+     .en(REN1),
+     .d(WA1),
+     .q(WA1Q));
 
   flopenr #(1) WEN1Reg(.clk(clk),
-		       .reset(reset),
-		       .en(1'b1),
-		       .d(WEN1),
-		       .q(WEN1Q));
+         .reset(reset),
+         .en(1'b1),
+         .d(WEN1),
+         .q(WEN1Q));
   
   flopenr #(WIDTH) WD1Reg(.clk(clk),
-			  .reset(reset),
-			  .en(REN1),
-			  .d(WD1),
-			  .q(WD1Q));
+     .reset(reset),
+     .en(REN1),
+     .d(WD1),
+     .q(WD1Q));
   // read port
   assign RD1 = mem[RA1Q];
 
-  genvar 		    index;
+  genvar       index;
   
   // write port
   generate
     for (index = 0; index < WIDTH; index = index + 1) begin:bitwrite
       always_ff @ (posedge clk) begin
-	      if (WEN1Q & BitWEN1[index]) begin
-	        mem[WA1Q][index] <= WD1Q[index];
-	      end
+       if (WEN1Q & BitWEN1[index]) begin
+         mem[WA1Q][index] <= WD1Q[index];
+       end
       end
     end
   endgenerate
diff --git a/wally-pipelined/src/ifu/bpred.sv b/wally-pipelined/src/ifu/bpred.sv
index c0fd17fc8..3121e725c 100644
--- a/wally-pipelined/src/ifu/bpred.sv
+++ b/wally-pipelined/src/ifu/bpred.sv
@@ -29,43 +29,43 @@
 `include "wally-config.vh"
 
 module bpred 
-  (input logic clk, reset,
-   input logic 		    StallF, StallD, StallE, 
-   input logic 		    FlushF, FlushD, FlushE,
+  (input logic              clk, reset,
+   input logic              StallF, StallD, StallE, 
+   input logic              FlushF, FlushD, FlushE,
    // Fetch stage
    // the prediction
    input logic [`XLEN-1:0]  PCNextF, // *** forgot to include this one on the I/O list
    output logic [`XLEN-1:0] BPPredPCF,
-   output logic 	    SelBPPredF,
+   output logic             SelBPPredF,
    // Update Predictor
    input logic [`XLEN-1:0]  PCE, // The address of the currently executing instruction
    // 1 hot encoding
    // return, jump register, jump, branch
    // *** after reviewing the compressed instruction set I am leaning towards having the btb predict the instruction class.
    // *** the specifics of how this is encode is subject to change.
-   input logic 		    PCSrcE, // AKA Branch Taken
+   input logic              PCSrcE, // AKA Branch Taken
    // Signals required to check the branch prediction accuracy.
    input logic [`XLEN-1:0]  PCTargetE, // The branch destination if the branch is taken.
    input logic [`XLEN-1:0]  PCD, // The address the branch predictor took.
    input logic [`XLEN-1:0]  PCLinkE, // The address following the branch instruction. (AKA Fall through address)
-   input logic [4:0] 	    InstrClassE,
+   input logic [4:0]        InstrClassE,
    // Report branch prediction status
-   output logic 	    BPPredWrongE,
-   output logic 	    BPPredDirWrongE,
-   output logic 	    BTBPredPCWrongE,
-   output logic 	    RASPredPCWrongE,
-   output logic 	    BPPredClassNonCFIWrongE
+   output logic             BPPredWrongE,
+   output logic             BPPredDirWrongE,
+   output logic             BTBPredPCWrongE,
+   output logic             RASPredPCWrongE,
+   output logic             BPPredClassNonCFIWrongE
    );
 
-  logic 		    BTBValidF;
-  logic [1:0] 		    BPPredF, BPPredD, BPPredE, UpdateBPPredE;
+  logic                     BTBValidF;
+  logic [1:0]               BPPredF, BPPredD, BPPredE, UpdateBPPredE;
 
-  logic [4:0] 		    BPInstrClassF, BPInstrClassD, BPInstrClassE;
-  logic [`XLEN-1:0] 	    BTBPredPCF, RASPCF;
-  logic 		    TargetWrongE;
-  logic 		    FallThroughWrongE;
-  logic 		    PredictionPCWrongE;
-  logic 		    PredictionInstrClassWrongE;
+  logic [4:0]               BPInstrClassF, BPInstrClassD, BPInstrClassE;
+  logic [`XLEN-1:0]         BTBPredPCF, RASPCF;
+  logic                     TargetWrongE;
+  logic                     FallThroughWrongE;
+  logic                     PredictionPCWrongE;
+  logic                     PredictionInstrClassWrongE;
   
 
   // Part 1 branch direction prediction
@@ -73,69 +73,69 @@ module bpred
   generate
     if (`BPTYPE == "BPTWOBIT") begin:Predictor
       twoBitPredictor DirPredictor(.clk(clk),
-				   .reset(reset),
-				   .StallF(StallF),
-				   .LookUpPC(PCNextF),
-				   .Prediction(BPPredF),
-				   // update
-				   .UpdatePC(PCE),
-				   .UpdateEN(InstrClassE[0] & ~StallE),
-				   .UpdatePrediction(UpdateBPPredE));
+       .reset(reset),
+       .StallF(StallF),
+       .LookUpPC(PCNextF),
+       .Prediction(BPPredF),
+       // update
+       .UpdatePC(PCE),
+       .UpdateEN(InstrClassE[0] & ~StallE),
+       .UpdatePrediction(UpdateBPPredE));
 
     end else if (`BPTYPE == "BPGLOBAL") begin:Predictor
 
       globalHistoryPredictor DirPredictor(.clk(clk),
-					  .reset(reset),
-					  .*, // Stalls and flushes
-					  .PCNextF(PCNextF),
-					  .BPPredF(BPPredF),
-					  // update
-					  .InstrClassE(InstrClassE),
-					  .BPInstrClassE(BPInstrClassE),
-					  .BPPredDirWrongE(BPPredDirWrongE),
-					  .PCE(PCE),
-					  .PCSrcE(PCSrcE),
-					  .UpdateBPPredE(UpdateBPPredE));
+       .reset(reset),
+       .*, // Stalls and flushes
+       .PCNextF(PCNextF),
+       .BPPredF(BPPredF),
+       // update
+       .InstrClassE(InstrClassE),
+       .BPInstrClassE(BPInstrClassE),
+       .BPPredDirWrongE(BPPredDirWrongE),
+       .PCE(PCE),
+       .PCSrcE(PCSrcE),
+       .UpdateBPPredE(UpdateBPPredE));
     end else if (`BPTYPE == "BPGSHARE") begin:Predictor
 
       gsharePredictor DirPredictor(.clk(clk),
-					  .reset(reset),
-					  .*, // Stalls and flushes
-					  .PCNextF(PCNextF),
-					  .BPPredF(BPPredF),
-					  // update
-					  .InstrClassE(InstrClassE),
-					  .BPInstrClassE(BPInstrClassE),
-					  .BPPredDirWrongE(BPPredDirWrongE),
-					  .PCE(PCE),
-					  .PCSrcE(PCSrcE),
-					  .UpdateBPPredE(UpdateBPPredE));
+       .reset(reset),
+       .*, // Stalls and flushes
+       .PCNextF(PCNextF),
+       .BPPredF(BPPredF),
+       // update
+       .InstrClassE(InstrClassE),
+       .BPInstrClassE(BPInstrClassE),
+       .BPPredDirWrongE(BPPredDirWrongE),
+       .PCE(PCE),
+       .PCSrcE(PCSrcE),
+       .UpdateBPPredE(UpdateBPPredE));
     end 
     else if (`BPTYPE == "BPLOCALPAg") begin:Predictor
 
       localHistoryPredictor DirPredictor(.clk(clk),
-				   .reset(reset),
-				   .*, // Stalls and flushes
-				   .LookUpPC(PCNextF),
-				   .Prediction(BPPredF),
-				   // update
-				   .UpdatePC(PCE),
-				   .UpdateEN(InstrClassE[0] & ~StallE),
-				   .PCSrcE(PCSrcE),
-				   .UpdatePrediction(UpdateBPPredE));
+       .reset(reset),
+       .*, // Stalls and flushes
+       .LookUpPC(PCNextF),
+       .Prediction(BPPredF),
+       // update
+       .UpdatePC(PCE),
+       .UpdateEN(InstrClassE[0] & ~StallE),
+       .PCSrcE(PCSrcE),
+       .UpdatePrediction(UpdateBPPredE));
     end 
     else if (`BPTYPE == "BPLOCALPAg") begin:Predictor
 
       localHistoryPredictor DirPredictor(.clk(clk),
-				   .reset(reset),
-				   .*, // Stalls and flushes
-				   .LookUpPC(PCNextF),
-				   .Prediction(BPPredF),
-				   // update
-				   .UpdatePC(PCE),
-				   .UpdateEN(InstrClassE[0] & ~StallE),
-				   .PCSrcE(PCSrcE),
-				   .UpdatePrediction(UpdateBPPredE));
+       .reset(reset),
+       .*, // Stalls and flushes
+       .LookUpPC(PCNextF),
+       .Prediction(BPPredF),
+       // update
+       .UpdatePC(PCE),
+       .UpdateEN(InstrClassE[0] & ~StallE),
+       .PCSrcE(PCSrcE),
+       .UpdatePrediction(UpdateBPPredE));
     end 
   endgenerate
 
@@ -146,9 +146,9 @@ module bpred
   // For a 2 bit table this is the prediction count.
 
   assign SelBPPredF = ((BPInstrClassF[0] & BPPredF[1] & BTBValidF) | 
-		       BPInstrClassF[3] |
-		       (BPInstrClassF[2] & BTBValidF) | 
-		       BPInstrClassF[1] & BTBValidF) ;
+         BPInstrClassF[3] |
+         (BPInstrClassF[2] & BTBValidF) | 
+         BPInstrClassF[1] & BTBValidF) ;
 
 
   // Part 2 Branch target address prediction
@@ -156,28 +156,28 @@ module bpred
 
   // *** getting to many false positivies from the BTB, we need a partial TAG to reduce this.
   BTBPredictor TargetPredictor(.clk(clk),
-			       .reset(reset),
-			       .*, // Stalls and flushes
-			       .LookUpPC(PCNextF),
-			       .TargetPC(BTBPredPCF),
-			       .InstrClass(BPInstrClassF),
-			       .Valid(BTBValidF),
-			       // update
-			       .UpdateEN((|InstrClassE | (PredictionInstrClassWrongE)) & ~StallE),
-			       .UpdatePC(PCE),
-			       .UpdateTarget(PCTargetE),
-			       .UpdateInvalid(PredictionInstrClassWrongE),
-			       .UpdateInstrClass(InstrClassE));
+          .reset(reset),
+          .*, // Stalls and flushes
+          .LookUpPC(PCNextF),
+          .TargetPC(BTBPredPCF),
+          .InstrClass(BPInstrClassF),
+          .Valid(BTBValidF),
+          // update
+          .UpdateEN((|InstrClassE | (PredictionInstrClassWrongE)) & ~StallE),
+          .UpdatePC(PCE),
+          .UpdateTarget(PCTargetE),
+          .UpdateInvalid(PredictionInstrClassWrongE),
+          .UpdateInstrClass(InstrClassE));
 
   // Part 3 RAS
   // *** need to add the logic to restore RAS on flushes.  We will use incr for this.
   RASPredictor RASPredictor(.clk(clk),
-			    .reset(reset),
-			    .pop(BPInstrClassF[3] & ~StallF),
-			    .popPC(RASPCF),
-			    .push(InstrClassE[4] & ~StallE),
-			    .incr(1'b0),
-			    .pushPC(PCLinkE));
+       .reset(reset),
+       .pop(BPInstrClassF[3] & ~StallF),
+       .popPC(RASPCF),
+       .push(InstrClassE[4] & ~StallE),
+       .incr(1'b0),
+       .pushPC(PCLinkE));
 
   assign BPPredPCF = BPInstrClassF[3] ? RASPCF : BTBPredPCF;
   
@@ -187,31 +187,31 @@ module bpred
   // *** for other predictors will will be different.
   
   flopenr #(2) BPPredRegD(.clk(clk),
-			   .reset(reset),
-			   .en(~StallD),
-			   .d(BPPredF),
-			   .q(BPPredD));
+      .reset(reset),
+      .en(~StallD),
+      .d(BPPredF),
+      .q(BPPredD));
 
   flopenr #(2) BPPredRegE(.clk(clk),
-			   .reset(reset),
-			   .en(~StallE),
-			   .d(BPPredD),
-			   .q(BPPredE));
+      .reset(reset),
+      .en(~StallE),
+      .d(BPPredD),
+      .q(BPPredE));
 
   // pipeline the class
   flopenrc #(5) InstrClassRegD(.clk(clk),
-			       .reset(reset),
-			       .en(~StallD),
-			       .clear(FlushD),
-			       .d(BPInstrClassF),
-			       .q(BPInstrClassD));
+          .reset(reset),
+          .en(~StallD),
+          .clear(FlushD),
+          .d(BPInstrClassF),
+          .q(BPInstrClassD));
 
   flopenrc #(5) InstrClassRegE(.clk(clk),
-			       .reset(reset),
-			       .en(~StallE),
-			       .clear(FlushE),
-			       .d(BPInstrClassD),
-			       .q(BPInstrClassE));
+          .reset(reset),
+          .en(~StallE),
+          .clear(FlushE),
+          .d(BPInstrClassD),
+          .q(BPInstrClassE));
 
   
 
@@ -253,7 +253,7 @@ module bpred
   // Update predictors
 
   satCounter2 BPDirUpdate(.BrDir(PCSrcE),
-			  .OldState(BPPredE),
-			  .NewState(UpdateBPPredE));
+     .OldState(BPPredE),
+     .NewState(UpdateBPPredE));
 
 endmodule
diff --git a/wally-pipelined/src/ifu/decompress.sv b/wally-pipelined/src/ifu/decompress.sv
index 2f87a8b91..ca2b4e5aa 100644
--- a/wally-pipelined/src/ifu/decompress.sv
+++ b/wally-pipelined/src/ifu/decompress.sv
@@ -26,16 +26,16 @@
 `include "wally-config.vh"
 
 module decompress (
-  input  logic [31:0]     InstrRawD,
-  output logic [31:0]     InstrD,
-  output logic            IllegalCompInstrD);
+  input  logic [31:0] InstrRawD,
+  output logic [31:0] InstrD,
+  output logic        IllegalCompInstrD);
                         
-  logic [15:0] instr16;
-  logic [4:0] rds1, rs2, rs1p, rs2p, rds1p, rdp;
-  logic [11:0] immCILSP, immCILSPD, immCSS, immCSSD, immCL, immCLD, immCI, immCS, immCSD, immCB, immCIASP, immCIW;
-  logic [19:0] immCJ, immCILUI;
-  logic [5:0] immSH;
-  logic [1:0] op;
+  logic [15:0]        instr16;
+  logic [4:0]         rds1, rs2, rs1p, rs2p, rds1p, rdp;
+  logic [11:0]        immCILSP, immCILSPD, immCSS, immCSSD, immCL, immCLD, immCI, immCS, immCSD, immCB, immCIASP, immCIW;
+  logic [19:0]        immCJ, immCILUI;
+  logic [5:0]         immSH;
+  logic [1:0]         op;
     
   // if the system handles compressed instructions, decode appropriately
   generate
diff --git a/wally-pipelined/src/ifu/globalHistoryPredictor.sv b/wally-pipelined/src/ifu/globalHistoryPredictor.sv
index 9f0680ad0..7539f184d 100644
--- a/wally-pipelined/src/ifu/globalHistoryPredictor.sv
+++ b/wally-pipelined/src/ifu/globalHistoryPredictor.sv
@@ -30,35 +30,35 @@
 module globalHistoryPredictor
   #(parameter int k = 10
     )
-  (input logic clk,
-   input logic 		   reset,
-   input logic 		   StallF, StallE,
+  (input logic             clk,
+   input logic             reset,
+   input logic             StallF, StallE,
    input logic [`XLEN-1:0] PCNextF,
-   output logic [1:0] 	   BPPredF,
+   output logic [1:0]      BPPredF,
    // update
-   input logic [4:0] 	   InstrClassE,
-   input logic [4:0] 	   BPInstrClassE,
-   input logic [4:0] 	   BPInstrClassD,
-   input logic [4:0] 	   BPInstrClassF, 
-   input logic 		   BPPredDirWrongE,
+   input logic [4:0]       InstrClassE,
+   input logic [4:0]       BPInstrClassE,
+   input logic [4:0]       BPInstrClassD,
+   input logic [4:0]       BPInstrClassF, 
+   input logic             BPPredDirWrongE,
 
    input logic [`XLEN-1:0] PCE,
-   input logic 		   PCSrcE,
-   input logic [1:0] 	   UpdateBPPredE
+   input logic             PCSrcE,
+   input logic [1:0]       UpdateBPPredE
   
    );
-  logic [k+1:0] 	   GHR, GHRNext;
-  logic [k-1:0] 	   PHTUpdateAdr, PHTUpdateAdr0, PHTUpdateAdr1;
-  logic 		   PHTUpdateEN;
-  logic 		   BPClassWrongNonCFI;
-  logic 		   BPClassWrongCFI;
-  logic 		   BPClassRightNonCFI;
-  logic 		   BPClassRightBPWrong;
-  logic 		   BPClassRightBPRight;
+  logic [k+1:0]            GHR, GHRNext;
+  logic [k-1:0]            PHTUpdateAdr, PHTUpdateAdr0, PHTUpdateAdr1;
+  logic                    PHTUpdateEN;
+  logic                    BPClassWrongNonCFI;
+  logic                    BPClassWrongCFI;
+  logic                    BPClassRightNonCFI;
+  logic                    BPClassRightBPWrong;
+  logic                    BPClassRightBPRight;
 
-  logic [6:0] 		   GHRMuxSel;
-  logic 		   GHRUpdateEN;
-  logic [k-1:0] 	   GHRLookup;
+  logic [6:0]              GHRMuxSel;
+  logic                    GHRUpdateEN;
+  logic [k-1:0]            GHRLookup;
 
   assign BPClassRightNonCFI = ~BPInstrClassE[0] & ~InstrClassE[0];
   assign BPClassWrongCFI = ~BPInstrClassE[0] & InstrClassE[0];
@@ -92,10 +92,10 @@ module globalHistoryPredictor
   end
 
   flopenr #(k+2) GlobalHistoryRegister(.clk(clk),
-				       .reset(reset),
-				       .en((GHRUpdateEN)),
-				       .d(GHRNext),
-				       .q(GHR));
+           .reset(reset),
+           .en((GHRUpdateEN)),
+           .d(GHRNext),
+           .q(GHR));
 
   // if actively updating the GHR at the time of prediction we want to us
   // GHRNext as the lookup rather than GHR.
@@ -109,14 +109,14 @@ module globalHistoryPredictor
   
   // Make Prediction by reading the correct address in the PHT and also update the new address in the PHT 
   SRAM2P1R1W #(k, 2) PHT(.clk(clk),
-			 .reset(reset),
-			 //.RA1(GHR[k-1:0]),
-			 .RA1(GHRLookup),
-			 .RD1(BPPredF),
-			 .REN1(~StallF),
-			 .WA1(PHTUpdateAdr),
-			 .WD1(UpdateBPPredE),
-			 .WEN1(PHTUpdateEN),
-			 .BitWEN1(2'b11));
+    .reset(reset),
+    //.RA1(GHR[k-1:0]),
+    .RA1(GHRLookup),
+    .RD1(BPPredF),
+    .REN1(~StallF),
+    .WA1(PHTUpdateAdr),
+    .WD1(UpdateBPPredE),
+    .WEN1(PHTUpdateEN),
+    .BitWEN1(2'b11));
 
 endmodule
diff --git a/wally-pipelined/src/ifu/gsharePredictor.sv b/wally-pipelined/src/ifu/gsharePredictor.sv
index 6da754176..eb7033183 100644
--- a/wally-pipelined/src/ifu/gsharePredictor.sv
+++ b/wally-pipelined/src/ifu/gsharePredictor.sv
@@ -30,35 +30,35 @@
 module gsharePredictor
   #(parameter int k = 10
     )
-  (input logic clk,
-   input logic 		   reset,
-   input logic 		   StallF, StallE,
+  (input logic             clk,
+   input logic             reset,
+   input logic             StallF, StallE,
    input logic [`XLEN-1:0] PCNextF,
-   output logic [1:0] 	   BPPredF,
+   output logic [1:0]      BPPredF,
    // update
-   input logic [4:0] 	   InstrClassE,
-   input logic [4:0] 	   BPInstrClassE,
-   input logic [4:0] 	   BPInstrClassD,
-   input logic [4:0] 	   BPInstrClassF, 
-   input logic 		   BPPredDirWrongE,
+   input logic [4:0]       InstrClassE,
+   input logic [4:0]       BPInstrClassE,
+   input logic [4:0]       BPInstrClassD,
+   input logic [4:0]       BPInstrClassF, 
+   input logic             BPPredDirWrongE,
 
    input logic [`XLEN-1:0] PCE,
-   input logic 		   PCSrcE,
-   input logic [1:0] 	   UpdateBPPredE
+   input logic             PCSrcE,
+   input logic [1:0]       UpdateBPPredE
   
    );
-  logic [k+1:0] 	   GHR, GHRNext;
-  logic [k-1:0] 	   PHTUpdateAdr, PHTUpdateAdr0, PHTUpdateAdr1;
-  logic 		   PHTUpdateEN;
-  logic 		   BPClassWrongNonCFI;
-  logic 		   BPClassWrongCFI;
-  logic 		   BPClassRightNonCFI;
-  logic 		   BPClassRightBPWrong;
-  logic 		   BPClassRightBPRight;
+  logic [k+1:0]            GHR, GHRNext;
+  logic [k-1:0]            PHTUpdateAdr, PHTUpdateAdr0, PHTUpdateAdr1;
+  logic                    PHTUpdateEN;
+  logic                    BPClassWrongNonCFI;
+  logic                    BPClassWrongCFI;
+  logic                    BPClassRightNonCFI;
+  logic                    BPClassRightBPWrong;
+  logic                    BPClassRightBPRight;
 
-  logic [6:0] 		   GHRMuxSel;
-  logic 		   GHRUpdateEN;
-  logic [k-1:0] 	   GHRLookup;
+  logic [6:0]              GHRMuxSel;
+  logic                    GHRUpdateEN;
+  logic [k-1:0]            GHRLookup;
 
   assign BPClassRightNonCFI = ~BPInstrClassE[0] & ~InstrClassE[0];
   assign BPClassWrongCFI = ~BPInstrClassE[0] & InstrClassE[0];
@@ -92,10 +92,10 @@ module gsharePredictor
   end
 
   flopenr #(k+2) GlobalHistoryRegister(.clk(clk),
-				       .reset(reset),
-				       .en((GHRUpdateEN)),
-				       .d(GHRNext),
-				       .q(GHR));
+           .reset(reset),
+           .en((GHRUpdateEN)),
+           .d(GHRNext),
+           .q(GHR));
 
   // if actively updating the GHR at the time of prediction we want to us
   // GHRNext as the lookup rather than GHR.
@@ -109,14 +109,14 @@ module gsharePredictor
   
   // Make Prediction by reading the correct address in the PHT and also update the new address in the PHT 
   SRAM2P1R1W #(k, 2) PHT(.clk(clk),
-			 .reset(reset),
-			 //.RA1(GHR[k-1:0]),
-			 .RA1(GHRLookup ^ PCNextF[k:1]),
-			 .RD1(BPPredF),
-			 .REN1(~StallF),
-			 .WA1(PHTUpdateAdr ^ PCE[k:1]),
-			 .WD1(UpdateBPPredE),
-			 .WEN1(PHTUpdateEN),
-			 .BitWEN1(2'b11));
+    .reset(reset),
+    //.RA1(GHR[k-1:0]),
+    .RA1(GHRLookup ^ PCNextF[k:1]),
+    .RD1(BPPredF),
+    .REN1(~StallF),
+    .WA1(PHTUpdateAdr ^ PCE[k:1]),
+    .WD1(UpdateBPPredE),
+    .WEN1(PHTUpdateEN),
+    .BitWEN1(2'b11));
 
 endmodule // gsharePredictor
diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv
index 0582395b3..9ddb39019 100644
--- a/wally-pipelined/src/ifu/ifu.sv
+++ b/wally-pipelined/src/ifu/ifu.sv
@@ -27,80 +27,80 @@
 `include "wally-config.vh"
 
 module ifu (
-  input logic 		      clk, reset,
-  input logic 		      StallF, StallD, StallE, StallM, StallW,
-  input logic 		      FlushF, FlushD, FlushE, FlushM, FlushW,
+  input logic                  clk, reset,
+  input logic                  StallF, StallD, StallE, StallM, StallW,
+  input logic                  FlushF, FlushD, FlushE, FlushM, FlushW,
   // Fetch
-  input logic [`XLEN-1:0]     InstrInF,
-  input logic 		      InstrAckF,
-  output logic [`XLEN-1:0]    PCF, 
-  output logic [`PA_BITS-1:0] InstrPAdrF,
-  output logic 		      InstrReadF,
-  output logic 		      ICacheStallF,
+  input logic [`XLEN-1:0]      InstrInF,
+  input logic                  InstrAckF,
+  output logic [`XLEN-1:0]     PCF, 
+  output logic [`PA_BITS-1:0]  InstrPAdrF,
+  output logic                 InstrReadF,
+  output logic                 ICacheStallF,
   // Execute
-  output logic [`XLEN-1:0]    PCLinkE,
-  input logic 		      PCSrcE, 
-  input logic [`XLEN-1:0]     PCTargetE,
-  output logic [`XLEN-1:0]    PCE,
-  output logic 		      BPPredWrongE, 
+  output logic [`XLEN-1:0]     PCLinkE,
+  input logic                  PCSrcE, 
+  input logic [`XLEN-1:0]      PCTargetE,
+  output logic [`XLEN-1:0]     PCE,
+  output logic                 BPPredWrongE, 
   // Mem
-  input logic 		      RetM, TrapM, 
-  input logic [`XLEN-1:0]     PrivilegedNextPCM, 
-  input logic                 InvalidateICacheM,
-  output logic [31:0] 	      InstrD, InstrM, 
-  output logic [`XLEN-1:0]    PCM, 
-  output logic [4:0] 	      InstrClassM,
-  output logic 		      BPPredDirWrongM,
-  output logic 		      BTBPredPCWrongM,
-  output logic 		      RASPredPCWrongM,
-  output logic 		      BPPredClassNonCFIWrongM,
+  input logic                  RetM, TrapM, 
+  input logic [`XLEN-1:0]      PrivilegedNextPCM, 
+  input logic                  InvalidateICacheM,
+  output logic [31:0]          InstrD, InstrM, 
+  output logic [`XLEN-1:0]     PCM, 
+  output logic [4:0]           InstrClassM,
+  output logic                 BPPredDirWrongM,
+  output logic                 BTBPredPCWrongM,
+  output logic                 RASPredPCWrongM,
+  output logic                 BPPredClassNonCFIWrongM,
   // Writeback
   // output logic [`XLEN-1:0] PCLinkW,
   // Faults
-  input logic 		      IllegalBaseInstrFaultD,
-  output logic 		      ITLBInstrPageFaultF,
-  output logic 		      IllegalIEUInstrFaultD,
-  output logic 		      InstrMisalignedFaultM,
-  output logic [`XLEN-1:0]    InstrMisalignedAdrM,
+  input logic                  IllegalBaseInstrFaultD,
+  output logic                 ITLBInstrPageFaultF,
+  output logic                 IllegalIEUInstrFaultD,
+  output logic                 InstrMisalignedFaultM,
+  output logic [`XLEN-1:0]     InstrMisalignedAdrM,
 
   
   // mmu management
-  input logic [1:0] 	      PrivilegeModeW,
-  input logic [`XLEN-1:0]     PTE,
-  input logic [1:0] 	      PageType,
-  input logic [`XLEN-1:0]     SATP_REGW,
-  input logic              STATUS_MXR, STATUS_SUM, STATUS_MPRV,
-  input logic  [1:0]       STATUS_MPP,
-  input logic 		      ITLBWriteF, ITLBFlushF,
-  input logic 		      WalkerInstrPageFaultF,
+  input logic [1:0]            PrivilegeModeW,
+  input logic [`XLEN-1:0]      PTE,
+  input logic [1:0]            PageType,
+  input logic [`XLEN-1:0]      SATP_REGW,
+  input logic                  STATUS_MXR, STATUS_SUM, STATUS_MPRV,
+  input logic  [1:0]           STATUS_MPP,
+  input logic                  ITLBWriteF, ITLBFlushF,
+  input logic                  WalkerInstrPageFaultF,
 
-  output logic 		      ITLBMissF,
+  output logic                 ITLBMissF,
 
   // pmp/pma (inside mmu) signals.  *** temporarily from AHB bus but eventually replace with internal versions pre H
-  input  var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
+  input  var logic [7:0]       PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
   input  var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0], 
 
-  output logic InstrAccessFaultF
+  output logic                 InstrAccessFaultF
 );
 
-  logic [`XLEN-1:0] PCCorrectE, UnalignedPCNextF, PCNextF;
-  logic             misaligned, BranchMisalignedFaultE, BranchMisalignedFaultM, TrapMisalignedFaultM;
-  logic             PrivilegedChangePCM;
-  logic             IllegalCompInstrD;
-  logic [`XLEN-1:0] PCPlus2or4F, PCLinkD;
-  logic [`XLEN-3:0] PCPlusUpperF;
-  logic             CompressedF;
-  logic [31:0]      InstrRawD, FinalInstrRawF;
-  logic [31:0] 	    InstrE;
-  logic [`XLEN-1:0] PCD;
+  logic [`XLEN-1:0]            PCCorrectE, UnalignedPCNextF, PCNextF;
+  logic                        misaligned, BranchMisalignedFaultE, BranchMisalignedFaultM, TrapMisalignedFaultM;
+  logic                        PrivilegedChangePCM;
+  logic                        IllegalCompInstrD;
+  logic [`XLEN-1:0]            PCPlus2or4F, PCLinkD;
+  logic [`XLEN-3:0]            PCPlusUpperF;
+  logic                        CompressedF;
+  logic [31:0]                 InstrRawD, FinalInstrRawF;
+  logic [31:0]                 InstrE;
+  logic [`XLEN-1:0]            PCD;
 
   localparam [31:0]      nop = 32'h00000013; // instruction for NOP
-  logic 	    reset_q; // *** look at this later.
+  logic                        reset_q; // *** look at this later.
 
-  logic 	    BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE;
+  logic                        BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE;
   
-  logic [`PA_BITS-1:0] PCPFmmu, PCNextFPhys; // used to either truncate or expand PCPF and PCNextF into `PA_BITS width.
-  logic [`XLEN+1:0]    PCFExt;
+  logic [`PA_BITS-1:0]         PCPFmmu, PCNextFPhys; // used to either truncate or expand PCPF and PCNextF into `PA_BITS width.
+  logic [`XLEN+1:0]            PCFExt;
 
   generate
     if (`XLEN==32) begin
@@ -138,9 +138,9 @@ module ifu (
 
 
   // branch predictor signals
-  logic 	          SelBPPredF;
-  logic [`XLEN-1:0] BPPredPCF, PCNext0F, PCNext1F, PCNext2F, PCNext3F;
-  logic [4:0] 	    InstrClassD, InstrClassE;
+  logic                        SelBPPredF;
+  logic [`XLEN-1:0]            BPPredPCF, PCNext0F, PCNext1F, PCNext2F, PCNext3F;
+  logic [4:0]                  InstrClassD, InstrClassE;
   
 
   // *** put memory interface on here, InstrF becomes output
@@ -149,10 +149,10 @@ module ifu (
   // assign InstrReadF = 1; // *** & ICacheMissF; add later
 
   icache icache(.*,
-		.PCNextF(PCNextFPhys),
-		.PCPF(PCPFmmu),
-		.WalkerInstrPageFaultF,
-		.InvalidateICacheM);
+  .PCNextF(PCNextFPhys),
+  .PCPF(PCPFmmu),
+  .WalkerInstrPageFaultF,
+  .InvalidateICacheM);
   
   flopenl #(32) AlignedInstrRawDFlop(clk, reset | reset_q, ~StallD, FlushD ? nop : FinalInstrRawF, nop, InstrRawD);
 
@@ -160,33 +160,33 @@ module ifu (
   assign PrivilegedChangePCM = RetM | TrapM;
 
   mux2 #(`XLEN) pcmux0(.d0(PCPlus2or4F),
-		       .d1(BPPredPCF),
-		       .s(SelBPPredF),
-		       .y(PCNext0F));
+         .d1(BPPredPCF),
+         .s(SelBPPredF),
+         .y(PCNext0F));
 
   mux2 #(`XLEN) pcmux1(.d0(PCNext0F),
-		       .d1(PCCorrectE),
-		       .s(BPPredWrongE),
-		       .y(PCNext1F));
+         .d1(PCCorrectE),
+         .s(BPPredWrongE),
+         .y(PCNext1F));
 
   mux2 #(`XLEN) pcmux2(.d0(PCNext1F),
-		       .d1(PCE),
-		       .s(InvalidateICacheM),
-		       .y(PCNext2F));
+         .d1(PCE),
+         .s(InvalidateICacheM),
+         .y(PCNext2F));
   
   mux2 #(`XLEN) pcmux3(.d0(PCNext2F),
-		       .d1(PrivilegedNextPCM),
-		       .s(PrivilegedChangePCM),
-		       .y(PCNext3F));
+         .d1(PrivilegedNextPCM),
+         .s(PrivilegedChangePCM),
+         .y(PCNext3F));
 
   mux2 #(`XLEN) pcmux4(.d0(PCNext3F),
-		       .d1(`RESET_VECTOR),
-		       .s(reset_q),
-		       .y(UnalignedPCNextF)); 
+         .d1(`RESET_VECTOR),
+         .s(reset_q),
+         .y(UnalignedPCNextF)); 
  
   flop #(1) resetReg (.clk(clk),
-		      .d(reset),
-		      .q(reset_q));
+        .d(reset),
+        .q(reset_q));
   
   
   assign  PCNextF = {UnalignedPCNextF[`XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment
@@ -197,20 +197,20 @@ module ifu (
     if (`BPRED_ENABLED == 1) begin : bpred
       // I am making the port connection explicit for now as I want to see them and they will be changing.
       bpred bpred(.*,
-		  .PCNextF(PCNextF),
-		  .BPPredPCF(BPPredPCF),
-		  .SelBPPredF(SelBPPredF),
-		  .PCE(PCE),
-		  .PCSrcE(PCSrcE),
-		  .PCTargetE(PCTargetE),
-		  .PCD(PCD),
-		  .PCLinkE(PCLinkE),
-		  .InstrClassE(InstrClassE),
-		  .BPPredWrongE(BPPredWrongE),
- 		  .BPPredDirWrongE(BPPredDirWrongE),
- 		  .BTBPredPCWrongE(BTBPredPCWrongE),
- 		  .RASPredPCWrongE(RASPredPCWrongE),
- 		  .BPPredClassNonCFIWrongE(BPPredClassNonCFIWrongE));
+    .PCNextF(PCNextF),
+    .BPPredPCF(BPPredPCF),
+    .SelBPPredF(SelBPPredF),
+    .PCE(PCE),
+    .PCSrcE(PCSrcE),
+    .PCTargetE(PCTargetE),
+    .PCD(PCD),
+    .PCLinkE(PCLinkE),
+    .InstrClassE(InstrClassE),
+    .BPPredWrongE(BPPredWrongE),
+     .BPPredDirWrongE(BPPredDirWrongE),
+     .BTBPredPCWrongE(BTBPredPCWrongE),
+     .RASPredPCWrongE(RASPredPCWrongE),
+     .BPPredClassNonCFIWrongE(BPPredClassNonCFIWrongE));
     end else begin : bpred
       assign BPPredPCF = {`XLEN{1'b0}};
       assign SelBPPredF = 1'b0;
@@ -274,25 +274,25 @@ module ifu (
   flopenr #(`XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM);
 
   flopenrc #(5) InstrClassRegE(.clk(clk),
-			       .reset(reset),
-			       .en(~StallE),
-			       .clear(FlushE),
-			       .d(InstrClassD),
-			       .q(InstrClassE));
+          .reset(reset),
+          .en(~StallE),
+          .clear(FlushE),
+          .d(InstrClassD),
+          .q(InstrClassE));
 
   flopenrc #(5) InstrClassRegM(.clk(clk),
-			       .reset(reset),
-			       .en(~StallM),
-			       .clear(FlushM),
-			       .d(InstrClassE),
-			       .q(InstrClassM));
+          .reset(reset),
+          .en(~StallM),
+          .clear(FlushM),
+          .d(InstrClassE),
+          .q(InstrClassM));
 
   flopenrc #(4) BPPredWrongRegM(.clk(clk),
-			       .reset(reset),
-			       .en(~StallM),
-			       .clear(FlushM),
-			       .d({BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE}),
-			       .q({BPPredDirWrongM, BTBPredPCWrongM, RASPredPCWrongM, BPPredClassNonCFIWrongM}));
+          .reset(reset),
+          .en(~StallM),
+          .clear(FlushM),
+          .d({BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE}),
+          .q({BPPredDirWrongM, BTBPredPCWrongM, RASPredPCWrongM, BPPredClassNonCFIWrongM}));
 
   // seems like there should be a lower-cost way of doing this PC+2 or PC+4 for JAL.  
   // either have ALU compute PC+2/4 and feed into ALUResult input of ResultMux or
diff --git a/wally-pipelined/src/ifu/localHistoryPredictor.sv b/wally-pipelined/src/ifu/localHistoryPredictor.sv
index b951704a0..4001723df 100644
--- a/wally-pipelined/src/ifu/localHistoryPredictor.sv
+++ b/wally-pipelined/src/ifu/localHistoryPredictor.sv
@@ -31,24 +31,24 @@ module localHistoryPredictor
   #(  parameter int m = 6, // 2^m = number of local history branches
       parameter int k = 10 // number of past branches stored
       )
-  (input logic clk,
-   input logic 		   reset,
-   input logic 		   StallF,  StallE, FlushF,
+  (input logic             clk,
+   input logic             reset,
+   input logic             StallF,  StallE, FlushF,
    input logic [`XLEN-1:0] LookUpPC,
-   output logic [1:0] 	   Prediction,
+   output logic [1:0]      Prediction,
    // update
    input logic [`XLEN-1:0] UpdatePC,
-   input logic 		   UpdateEN, PCSrcE, 
-   input logic [1:0] 	   UpdatePrediction
+   input logic             UpdateEN, PCSrcE, 
+   input logic [1:0]       UpdatePrediction
   
    );
 
-  logic [2**m-1:0][k-1:0]  LHRNextF;
-  logic [k-1:0] 	   LHRF, ForwardLHRNext, LHRFNext;
-  logic [m-1:0] 	   LookUpPCIndex, UpdatePCIndex;
-  logic [1:0] 		   PredictionMemory;
-  logic 		   DoForwarding, DoForwardingF, DoForwardingPHT, DoForwardingPHTF;
-  logic [1:0] 		   UpdatePredictionF;
+  logic [2**m-1:0]         [k-1:0]  LHRNextF;
+  logic [k-1:0]            LHRF, ForwardLHRNext, LHRFNext;
+  logic [m-1:0]            LookUpPCIndex, UpdatePCIndex;
+  logic [1:0]              PredictionMemory;
+  logic                    DoForwarding, DoForwardingF, DoForwardingPHT, DoForwardingPHTF;
+  logic [1:0]              UpdatePredictionF;
 
   assign LHRFNext = {PCSrcE, LHRF[k-1:1]}; 
   assign UpdatePCIndex = {UpdatePC[m+1] ^ UpdatePC[1], UpdatePC[m:2]};
@@ -65,15 +65,15 @@ module localHistoryPredictor
   //                 .WEN1(UpdateEN),
   //                 .BitWEN1(2'b11));  
 
-  genvar 		   index;
+  genvar      index;
   generate
     for (index = 0; index < 2**m; index = index +1) begin:localhist
       
       flopenr #(k) LocalHistoryRegister(.clk(clk),
-					.reset(reset),
-					.en(UpdateEN && (index == UpdatePCIndex)),
-					.d(LHRFNext),
-					.q(LHRNextF[index]));
+     .reset(reset),
+     .en(UpdateEN && (index == UpdatePCIndex)),
+     .d(LHRFNext),
+     .q(LHRNextF[index]));
     end 
   endgenerate
 
@@ -86,14 +86,14 @@ module localHistoryPredictor
   // LHR referes to the address that the past k branches points to in the prediction stage 
   // LHRE refers to the address that the past k branches points to in the exectution stage
   SRAM2P1R1W #(k, 2) PHT(.clk(clk), 
-			 .reset(reset),
-			 .RA1(ForwardLHRNext),
-			 .RD1(PredictionMemory),
-			 .REN1(~StallF),
-			 .WA1(LHRFNext),
-			 .WD1(UpdatePrediction),
-			 .WEN1(UpdateEN),
-			 .BitWEN1(2'b11));
+    .reset(reset),
+    .RA1(ForwardLHRNext),
+    .RD1(PredictionMemory),
+    .REN1(~StallF),
+    .WA1(LHRFNext),
+    .WD1(UpdatePrediction),
+    .WEN1(UpdateEN),
+    .BitWEN1(2'b11));
 
 
   
@@ -102,24 +102,24 @@ module localHistoryPredictor
   // register the update value and the forwarding signal into the Fetch stage
   // TODO: add stall logic ***
   flopr #(1) DoForwardingReg(.clk(clk),
-			     .reset(reset),
-			     .d(DoForwardingPHT),
-			     .q(DoForwardingPHTF));
+        .reset(reset),
+        .d(DoForwardingPHT),
+        .q(DoForwardingPHTF));
   
   flopr #(2) UpdatePredictionReg(.clk(clk),
-				 .reset(reset),
-				 .d(UpdatePrediction),
-				 .q(UpdatePredictionF));
+     .reset(reset),
+     .d(UpdatePrediction),
+     .q(UpdatePredictionF));
 
   assign Prediction = DoForwardingPHTF ? UpdatePredictionF : PredictionMemory;
   
   //pipeline for LHR
   flopenrc #(k) LHRFReg(.clk(clk),
-			.reset(reset),
-			.en(~StallF),
-			.clear(FlushF),
-			.d(ForwardLHRNext),
-			.q(LHRF));
+   .reset(reset),
+   .en(~StallF),
+   .clear(FlushF),
+   .d(ForwardLHRNext),
+   .q(LHRF));
   /*
    flopenrc #(k) LHRDReg(.clk(clk),
    .reset(reset),
diff --git a/wally-pipelined/src/ifu/satCounter2.sv b/wally-pipelined/src/ifu/satCounter2.sv
index 33a842dcc..30c8969a9 100644
--- a/wally-pipelined/src/ifu/satCounter2.sv
+++ b/wally-pipelined/src/ifu/satCounter2.sv
@@ -28,28 +28,28 @@
 `include "wally-config.vh"
 
 module satCounter2
-  (input logic BrDir,
-   input logic [1:0] OldState,
+  (input logic        BrDir,
+   input logic [1:0]  OldState,
    output logic [1:0] NewState
    );
 
   always_comb begin
     case(OldState)
       2'b00: begin
-	if(BrDir) NewState = 2'b01;
-	else NewState = 2'b00;
+ if(BrDir) NewState = 2'b01;
+ else NewState = 2'b00;
       end
       2'b01: begin
-	if(BrDir) NewState = 2'b10;
-	else NewState = 2'b00;
+ if(BrDir) NewState = 2'b10;
+ else NewState = 2'b00;
       end
       2'b10: begin
-	if(BrDir) NewState = 2'b11;
-	else NewState = 2'b01;
+ if(BrDir) NewState = 2'b11;
+ else NewState = 2'b01;
       end
       2'b11: begin
-	if(BrDir) NewState = 2'b11;
-	else NewState = 2'b10;
+ if(BrDir) NewState = 2'b11;
+ else NewState = 2'b10;
       end
     endcase
   end
diff --git a/wally-pipelined/src/ifu/twoBitPredictor.sv b/wally-pipelined/src/ifu/twoBitPredictor.sv
index af4942781..240975546 100644
--- a/wally-pipelined/src/ifu/twoBitPredictor.sv
+++ b/wally-pipelined/src/ifu/twoBitPredictor.sv
@@ -30,21 +30,21 @@
 module twoBitPredictor
   #(parameter int Depth = 10
     )
-  (input logic clk,
-   input logic 		   reset,
-   input logic 		   StallF,
+  (input logic             clk,
+   input logic             reset,
+   input logic             StallF,
    input logic [`XLEN-1:0] LookUpPC,
-   output logic [1:0] 	   Prediction,
+   output logic [1:0]      Prediction,
    // update
    input logic [`XLEN-1:0] UpdatePC,
-   input logic 		   UpdateEN,
-   input logic [1:0] 	   UpdatePrediction
+   input logic             UpdateEN,
+   input logic [1:0]       UpdatePrediction
    );
 
-  logic [Depth-1:0] 	   LookUpPCIndex, UpdatePCIndex;
-  logic [1:0] 		   PredictionMemory;
-  logic 		   DoForwarding, DoForwardingF;
-  logic [1:0] 		   UpdatePredictionF;
+  logic [Depth-1:0]        LookUpPCIndex, UpdatePCIndex;
+  logic [1:0]              PredictionMemory;
+  logic                    DoForwarding, DoForwardingF;
+  logic [1:0]              UpdatePredictionF;
   
 
   // hashing function for indexing the PC
@@ -56,14 +56,14 @@ module twoBitPredictor
 
 
   SRAM2P1R1W #(Depth, 2) PHT(.clk(clk),
-				.reset(reset),
-				.RA1(LookUpPCIndex),
-				.RD1(PredictionMemory),
-				.REN1(~StallF),
-				.WA1(UpdatePCIndex),
-				.WD1(UpdatePrediction),
-				.WEN1(UpdateEN),
-				.BitWEN1(2'b11));
+    .reset(reset),
+    .RA1(LookUpPCIndex),
+    .RD1(PredictionMemory),
+    .REN1(~StallF),
+    .WA1(UpdatePCIndex),
+    .WD1(UpdatePrediction),
+    .WEN1(UpdateEN),
+    .BitWEN1(2'b11));
 
   // need to forward when updating to the same address as reading.
   // first we compare to see if the update and lookup addreses are the same
@@ -71,14 +71,14 @@ module twoBitPredictor
 
   // register the update value and the forwarding signal into the Fetch stage
   flopr #(1) DoForwardingReg(.clk(clk),
-			     .reset(reset),
-			     .d(DoForwarding),
-			     .q(DoForwardingF));
+        .reset(reset),
+        .d(DoForwarding),
+        .q(DoForwardingF));
   
   flopr #(2) UpdatePredictionReg(.clk(clk),
-				 .reset(reset),
-				 .d(UpdatePrediction),
-				 .q(UpdatePredictionF));
+     .reset(reset),
+     .d(UpdatePrediction),
+     .q(UpdatePredictionF));
 
   assign Prediction = DoForwardingF ? UpdatePredictionF : PredictionMemory;
   
diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv
index 980166d95..ede4460e0 100644
--- a/wally-pipelined/src/wally/wallypipelinedhart.sv
+++ b/wally-pipelined/src/wally/wallypipelinedhart.sv
@@ -154,9 +154,30 @@ module wallypipelinedhart (
   logic 		    BreakpointFaultM, EcallFaultM;
 
   
-  ifu ifu(.InstrInF(InstrRData),
-	  .WalkerInstrPageFaultF(WalkerInstrPageFaultF),
-	  .*); // instruction fetch unit: PC, branch prediction, instruction cache
+  ifu ifu(
+    .clk, .reset, 
+    .StallF, .StallD, .StallE, .StallM, .StallW, 
+    .FlushF, .FlushD, .FlushE, .FlushM, .FlushW, 
+    .InstrInF(InstrRData), .InstrAckF, .PCF, .InstrPAdrF, .InstrReadF, .ICacheStallF, 
+    .PCLinkE, .PCSrcE, .PCTargetE, .PCE,
+    .BPPredWrongE, 
+    .RetM, .TrapM, 
+    .PrivilegedNextPCM, .InvalidateICacheM,
+    .InstrD, .InstrM, 
+    .PCM, .InstrClassM, 
+    .BPPredDirWrongM,.BTBPredPCWrongM,.RASPredPCWrongM, .BPPredClassNonCFIWrongM,
+    .IllegalBaseInstrFaultD, .ITLBInstrPageFaultF, .IllegalIEUInstrFaultD,
+    .InstrMisalignedFaultM, .InstrMisalignedAdrM,
+    .PrivilegeModeW, .PTE, .PageType, .SATP_REGW,
+    .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
+    .ITLBWriteF, .ITLBFlushF,
+    .WalkerInstrPageFaultF,
+    .ITLBMissF,
+    .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, 
+    .InstrAccessFaultF
+	  
+	  ); // instruction fetch unit: PC, branch prediction, instruction cache
+    
 
   ieu ieu(.*); // integer execution unit: integer register file, datapath and controller
 
diff --git a/wally-pipelined/testbench/testbench.sv b/wally-pipelined/testbench/testbench.sv
index d2c83a4c7..e7f7e1f5d 100644
--- a/wally-pipelined/testbench/testbench.sv
+++ b/wally-pipelined/testbench/testbench.sv
@@ -101,6 +101,7 @@ logic [3:0] dummy;
         "arch32priv":                     tests = arch32priv;
         "arch32c":      if (`C_SUPPORTED) tests = arch32c;
         "arch32m":      if (`M_SUPPORTED) tests = arch32m;
+        "arch32f":      if (`F_SUPPORTED) tests = arch32f;
         "imperas32i":                     tests = imperas32i;
         "imperas32p":                     tests = imperas32p;
         "imperas32mmu": if (`MEM_VIRTMEM) tests = imperas32mmu;
diff --git a/wally-pipelined/testbench/tests.vh b/wally-pipelined/testbench/tests.vh
index 5a8878f36..57de30760 100644
--- a/wally-pipelined/testbench/tests.vh
+++ b/wally-pipelined/testbench/tests.vh
@@ -668,158 +668,157 @@ string imperas32f[] = '{
     "rv32i_m/M/remu-01", "5010"
    };
 
-/*
   string arch32f[] = '{
+
     `RISCVARCHTEST,
-    "rv32i_m/M/div-01", "5010",
-    "fadd_b1-01", "",
-    "fadd_b10-01", "",
-    "fadd_b11-01", "",
-    "fadd_b12-01", "",
-    "fadd_b13-01", "",
-    "fadd_b2-01", "",
-    "fadd_b3-01", "",
-    "fadd_b4-01", "",
-    "fadd_b5-01", "",
-    "fadd_b7-01", "",
-    "fadd_b8-01", "",
-    "fclass_b1-01", "",
-    "fcvt.s.w_b25-01", "",
-    "fcvt.s.w_b26-01", "",
-    "fcvt.s.wu_b25-01", "",
-    "fcvt.s.wu_b26-01", "",
-    "fcvt.w.s_b1-01", "",
-    "fcvt.w.s_b22-01", "",
-    "fcvt.w.s_b23-01", "",
-    "fcvt.w.s_b24-01", "",
-    "fcvt.w.s_b27-01", "",
-    "fcvt.w.s_b28-01", "",
-    "fcvt.w.s_b29-01", "",
-    "fcvt.wu.s_b1-01", "",
-    "fcvt.wu.s_b22-01", "",
-    "fcvt.wu.s_b23-01", "",
-    "fcvt.wu.s_b24-01", "",
-    "fcvt.wu.s_b27-01", "",
-    "fcvt.wu.s_b28-01", "",
-    "fcvt.wu.s_b29-01", "",
-    "fdiv_b1-01", "",
-    "fdiv_b2-01", "",
-    "fdiv_b20-01", "",
-    "fdiv_b21-01", "",
-    "fdiv_b3-01", "",
-    "fdiv_b4-01", "",
-    "fdiv_b5-01", "",
-    "fdiv_b6-01", "",
-    "fdiv_b7-01", "",
-    "fdiv_b8-01", "",
-    "fdiv_b9-01", "",
-    "feq_b1-01", "",
-    "feq_b19-01", "",
-    "fle_b1-01", "",
-    "fle_b19-01", "",
-    "flt_b1-01", "",
-    "flt_b19-01", "",
-    "flw-align-01", "",
-    "fmadd_b1-01", "",
-    "fmadd_b14-01", "",
-    "fmadd_b15-01", "",
-    "fmadd_b16-01", "",
-    "fmadd_b17-01", "",
-    "fmadd_b18-01", "",
-    "fmadd_b2-01", "",
-    "fmadd_b3-01", "",
-    "fmadd_b4-01", "",
-    "fmadd_b5-01", "",
-    "fmadd_b6-01", "",
-    "fmadd_b7-01", "",
-    "fmadd_b8-01", "",
-    "fmax_b1-01", "",
-    "fmax_b19-01", "",
-    "fmin_b1-01", "",
-    "fmin_b19-01", "",
-    "fmsub_b1-01", "",
-    "fmsub_b14-01", "",
-    "fmsub_b15-01", "",
-    "fmsub_b16-01", "",
-    "fmsub_b17-01", "",
-    "fmsub_b18-01", "",
-    "fmsub_b2-01", "",
-    "fmsub_b3-01", "",
-    "fmsub_b4-01", "",
-    "fmsub_b5-01", "",
-    "fmsub_b6-01", "",
-    "fmsub_b7-01", "",
-    "fmsub_b8-01", "",
-    "fmul_b1-01", "",
-    "fmul_b2-01", "",
-    "fmul_b3-01", "",
-    "fmul_b4-01", "",
-    "fmul_b5-01", "",
-    "fmul_b6-01", "",
-    "fmul_b7-01", "",
-    "fmul_b8-01", "",
-    "fmul_b9-01", "",
-    "fmv.w.x_b25-01", "",
-    "fmv.w.x_b26-01", "",
-    "fmv.x.w_b1-01", "",
-    "fmv.x.w_b22-01", "",
-    "fmv.x.w_b23-01", "",
-    "fmv.x.w_b24-01", "",
-    "fmv.x.w_b27-01", "",
-    "fmv.x.w_b28-01", "",
-    "fmv.x.w_b29-01", "",
-    "fnmadd_b1-01", "",
-    "fnmadd_b14-01", "",
-    "fnmadd_b15-01", "",
-    "fnmadd_b16-01", "",
-    "fnmadd_b17-01", "",
-    "fnmadd_b18-01", "",
-    "fnmadd_b2-01", "",
-    "fnmadd_b3-01", "",
-    "fnmadd_b4-01", "",
-    "fnmadd_b5-01", "",
-    "fnmadd_b6-01", "",
-    "fnmadd_b7-01", "",
-    "fnmadd_b8-01", "",
-    "fnmsub_b1-01", "",
-    "fnmsub_b14-01", "",
-    "fnmsub_b15-01", "",
-    "fnmsub_b16-01", "",
-    "fnmsub_b17-01", "",
-    "fnmsub_b18-01", "",
-    "fnmsub_b2-01", "",
-    "fnmsub_b3-01", "",
-    "fnmsub_b4-01", "",
-    "fnmsub_b5-01", "",
-    "fnmsub_b6-01", "",
-    "fnmsub_b7-01", "",
-    "fnmsub_b8-01", "",
-    "fsgnj_b1-01", "",
-    "fsgnjn_b1-01", "",
-    "fsgnjx_b1-01", "",
-    "fsqrt_b1-01", "",
-    "fsqrt_b2-01", "",
-    "fsqrt_b20-01", "",
-    "fsqrt_b3-01", "",
-    "fsqrt_b4-01", "",
-    "fsqrt_b5-01", "",
-    "fsqrt_b7-01", "",
-    "fsqrt_b8-01", "",
-    "fsqrt_b9-01", "",
-    "fsub_b1-01", "",
-    "fsub_b10-01", "",
-    "fsub_b11-01", "",
-    "fsub_b12-01", "",
-    "fsub_b13-01", "",
-    "fsub_b2-01", "",
-    "fsub_b3-01", "",
-    "fsub_b4-01", "",
-    "fsub_b5-01", "",
-    "fsub_b7-01", "",
-    "fsub_b8-01", "",
-    "fsw-align-01, ""
+    // "rv32i_m/F/fadd_b1-01", "7220",
+    // "rv32i_m/F/fadd_b10-01", "2270", 
+    // "rv32i_m/F/fadd_b11-01", "3fb40",
+    // "rv32i_m/F/fadd_b12-01", "21b0",
+    // "rv32i_m/F/fadd_b13-01", "3660",
+    // "rv32i_m/F/fadd_b2-01", "38b0",
+    // "rv32i_m/F/fadd_b3-01", "b320",
+    // "rv32i_m/F/fadd_b4-01", "3480",
+    // "rv32i_m/F/fadd_b5-01", "3700",
+    // "rv32i_m/F/fadd_b7-01", "3520",
+    // "rv32i_m/F/fadd_b8-01", "104a0",
+    "rv32i_m/F/fclass_b1-01", "2090",
+    "rv32i_m/F/fcvt.s.w_b25-01", "20a0",
+    "rv32i_m/F/fcvt.s.w_b26-01", "3290",
+    "rv32i_m/F/fcvt.s.wu_b25-01", "20a0",
+    "rv32i_m/F/fcvt.s.wu_b26-01", "3290",
+//    "rv32i_m/F/fcvt.w.s_b1-01", "2090",
+//    "rv32i_m/F/fcvt.w.s_b22-01", "20b0",
+    // "rv32i_m/F/fcvt.w.s_b23-01", "20c0",
+    // "rv32i_m/F/fcvt.w.s_b24-01", "21b0",
+    // "rv32i_m/F/fcvt.w.s_b27-01", "2090",
+    // "rv32i_m/F/fcvt.w.s_b28-01", "2090",
+    // "rv32i_m/F/fcvt.w.s_b29-01", "2150",
+    // "rv32i_m/F/fcvt.wu.s_b1-01", "2090",
+    // "rv32i_m/F/fcvt.wu.s_b22-01", "20b0",
+    // "rv32i_m/F/fcvt.wu.s_b23-01", "20c0",
+    // "rv32i_m/F/fcvt.wu.s_b24-01", "21b0",
+    // "rv32i_m/F/fcvt.wu.s_b27-01", "2090",
+    // "rv32i_m/F/fcvt.wu.s_b28-01", "2090",
+    // "rv32i_m/F/fcvt.wu.s_b29-01", "2150",
+    // "rv32i_m/F/fdiv_b1-01", "7220",
+    // "rv32i_m/F/fdiv_b2-01", "2350",
+    // "rv32i_m/F/fdiv_b20-01", "38c0",
+    // "rv32i_m/F/fdiv_b21-01", "7540",
+    // "rv32i_m/F/fdiv_b3-01", "b320",
+    // "rv32i_m/F/fdiv_b4-01", "3480",
+    // "rv32i_m/F/fdiv_b5-01", "3700",
+    // "rv32i_m/F/fdiv_b6-01", "3480",
+    // "rv32i_m/F/fdiv_b7-01", "3520",
+    // "rv32i_m/F/fdiv_b8-01", "104a0",
+    // "rv32i_m/F/fdiv_b9-01", "d960",
+    // "rv32i_m/F/feq_b1-01", "6220",
+    // "rv32i_m/F/feq_b19-01", "a190",
+    // "rv32i_m/F/fle_b1-01", "6220",
+    // "rv32i_m/F/fle_b19-01", "a190",
+    // "rv32i_m/F/flt_b1-01", "6220",
+    // "rv32i_m/F/flt_b19-01", "8ee0",
+    "rv32i_m/F/flw-align-01", "2010",
+//    "rv32i_m/F/fmadd_b1-01", "96860",
+    "rv32i_m/F/fmadd_b14-01", "23d0",
+//--passes but is timeconsuming    "rv32i_m/F/fmadd_b15-01", "19bb30",
+    "rv32i_m/F/fmadd_b16-01", "39d0",
+    "rv32i_m/F/fmadd_b17-01", "39d0",
+//    "rv32i_m/F/fmadd_b18-01", "4d10",
+    "rv32i_m/F/fmadd_b2-01", "4d60",
+    "rv32i_m/F/fmadd_b3-01", "d4f0",
+    "rv32i_m/F/fmadd_b4-01", "3700",
+    "rv32i_m/F/fmadd_b5-01", "3ac0",
+    "rv32i_m/F/fmadd_b6-01", "3700",
+//    "rv32i_m/F/fmadd_b7-01", "d7f0",
+//    "rv32i_m/F/fmadd_b8-01", "13f30",
+    // "rv32i_m/F/fmax_b1-01", "7220",
+    // "rv32i_m/F/fmax_b19-01", "9e00",
+    // "rv32i_m/F/fmin_b1-01", "7220",
+    // "rv32i_m/F/fmin_b19-01", "9f20",
+    "rv32i_m/F/fmsub_b1-01", "96860",
+    "rv32i_m/F/fmsub_b14-01", "23d0",
+//    "rv32i_m/F/fmsub_b15-01", "19bb30",
+    "rv32i_m/F/fmsub_b16-01", "39d0",
+    "rv32i_m/F/fmsub_b17-01", "39d0",
+    "rv32i_m/F/fmsub_b18-01", "42d0",
+    "rv32i_m/F/fmsub_b2-01", "4d60",
+    "rv32i_m/F/fmsub_b3-01", "d4f0",
+    "rv32i_m/F/fmsub_b4-01", "3700",
+    "rv32i_m/F/fmsub_b5-01", "3ac0",
+    "rv32i_m/F/fmsub_b6-01", "3700",
+    "rv32i_m/F/fmsub_b7-01", "37f0",
+    "rv32i_m/F/fmsub_b8-01", "13f30",
+    "rv32i_m/F/fmul_b1-01", "7220",
+    "rv32i_m/F/fmul_b2-01", "38c0",
+    "rv32i_m/F/fmul_b3-01", "b320",
+    "rv32i_m/F/fmul_b4-01", "3480",
+    "rv32i_m/F/fmul_b5-01", "3700",
+    "rv32i_m/F/fmul_b6-01", "3480",
+    "rv32i_m/F/fmul_b7-01", "3520",
+    "rv32i_m/F/fmul_b8-01", "104a0",
+    "rv32i_m/F/fmul_b9-01", "d960",
+    "rv32i_m/F/fmv.w.x_b25-01", "2090",
+    "rv32i_m/F/fmv.w.x_b26-01", "2090",
+    "rv32i_m/F/fmv.x.w_b1-01", "2090",
+    "rv32i_m/F/fmv.x.w_b22-01", "2090",
+    "rv32i_m/F/fmv.x.w_b23-01", "2090",
+    "rv32i_m/F/fmv.x.w_b24-01", "2090",
+    "rv32i_m/F/fmv.x.w_b27-01", "2090",
+    "rv32i_m/F/fmv.x.w_b28-01", "2090",
+    "rv32i_m/F/fmv.x.w_b29-01", "2090",
+    "rv32i_m/F/fnmadd_b1-01", "96870",
+    "rv32i_m/F/fnmadd_b14-01", "23d0",
+// timeconsuming    "rv32i_m/F/fnmadd_b15-01", "19bb40",
+    "rv32i_m/F/fnmadd_b16-01", "39d0",
+    "rv32i_m/F/fnmadd_b17-01", "39d0",
+    "rv32i_m/F/fnmadd_b18-01", "4d10",
+    "rv32i_m/F/fnmadd_b2-01", "4d60",
+    "rv32i_m/F/fnmadd_b3-01", "d4f0",
+    "rv32i_m/F/fnmadd_b4-01", "3700",
+    "rv32i_m/F/fnmadd_b5-01", "3ac0",
+    "rv32i_m/F/fnmadd_b6-01", "3700",
+    "rv32i_m/F/fnmadd_b7-01", "37f0",
+    "rv32i_m/F/fnmadd_b8-01", "13f30",
+    "rv32i_m/F/fnmsub_b1-01", "96870",
+    "rv32i_m/F/fnmsub_b14-01", "23d0",
+// timeconsuming    "rv32i_m/F/fnmsub_b15-01", "19bb30",
+    "rv32i_m/F/fnmsub_b16-01", "39d0",
+    "rv32i_m/F/fnmsub_b17-01", "39d0",
+    "rv32i_m/F/fnmsub_b18-01", "4d10",
+    "rv32i_m/F/fnmsub_b2-01", "4d60",
+    "rv32i_m/F/fnmsub_b3-01", "4df0",
+    "rv32i_m/F/fnmsub_b4-01", "3700",
+    "rv32i_m/F/fnmsub_b5-01", "3ac0",
+    "rv32i_m/F/fnmsub_b6-01", "3700",
+    "rv32i_m/F/fnmsub_b7-01", "37f0",
+    "rv32i_m/F/fnmsub_b8-01", "13f30",
+    "rv32i_m/F/fsgnj_b1-01", "7220",
+    "rv32i_m/F/fsgnjn_b1-01", "7220",
+    "rv32i_m/F/fsgnjx_b1-01", "7220",
+    "rv32i_m/F/fsqrt_b1-01", "2090",
+    "rv32i_m/F/fsqrt_b2-01", "2090",
+    "rv32i_m/F/fsqrt_b20-01", "2090",
+    "rv32i_m/F/fsqrt_b3-01", "2090",
+    "rv32i_m/F/fsqrt_b4-01", "2090",
+    "rv32i_m/F/fsqrt_b5-01", "2090",
+    "rv32i_m/F/fsqrt_b7-01", "2090",
+    "rv32i_m/F/fsqrt_b8-01", "2090",
+    "rv32i_m/F/fsqrt_b9-01", "3310",
+    "rv32i_m/F/fsub_b1-01", "7220",
+    "rv32i_m/F/fsub_b10-01", "2250",
+    "rv32i_m/F/fsub_b11-01", "3fb40",
+    "rv32i_m/F/fsub_b12-01", "21b0",
+    "rv32i_m/F/fsub_b13-01", "3660",
+    "rv32i_m/F/fsub_b2-01", "38b0",
+    "rv32i_m/F/fsub_b3-01", "b320",
+    "rv32i_m/F/fsub_b4-01", "3480",
+    "rv32i_m/F/fsub_b5-01", "3700",
+    "rv32i_m/F/fsub_b7-01", "3520",
+    "rv32i_m/F/fsub_b8-01", "104a0",
+    "rv32i_m/F/fsw-align-01", "2010"
 };
-*/
+
 
   string arch32c[] = '{
     `RISCVARCHTEST,