Added debug signals to dcache.

wally-pipelined/src/cache/dcache.sv

@@ -64,13 +64,13 @@ module dcache
    input logic 		       WalkerPageFaultM, 
    output logic 	       MemAfterIWalkDone,
    // ahb side
-   output logic [`PA_BITS-1:0] AHBPAdr, // to ahb
+   (* mark_debug = "true" *)output logic [`PA_BITS-1:0] AHBPAdr, // to ahb
-   output logic 	       AHBRead,
+   (* mark_debug = "true" *)output logic 	       AHBRead,
-   output logic 	       AHBWrite,
+   (* mark_debug = "true" *)output logic 	       AHBWrite,
-   input logic 		       AHBAck, // from ahb
+   (* mark_debug = "true" *)input logic 		       AHBAck, // from ahb
-   input logic [`XLEN-1:0]     HRDATA, // from ahb
+   (* mark_debug = "true" *)input logic [`XLEN-1:0]     HRDATA, // from ahb
-   output logic [`XLEN-1:0]    HWDATA, // to ahb
+   (* mark_debug = "true" *)output logic [`XLEN-1:0]    HWDATA, // to ahb
-   output logic [2:0] 	       DCtoAHBSizeM
+   (* mark_debug = "true" *)output logic [2:0] 	       DCtoAHBSizeM
    );
 
 /*  localparam integer	       BLOCKLEN = 256;

wally-pipelined/src/cache/dcachefsm.sv

@@ -138,7 +138,7 @@ module dcachefsm
 		STATE_FLUSH_WRITE_BACK,
 		STATE_FLUSH_CLEAR_DIRTY} statetype;
 
-  statetype CurrState, NextState;
+  (* mark_debug = "true" *) statetype CurrState, NextState;
 
   assign AnyCPUReqM = |MemRWM | (|AtomicM);
   assign CntEn = PreCntEn & AHBAck;