From fe22d4544f7a28e46854e0452e66917441165144 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 29 Dec 2021 10:58:02 -0600 Subject: [PATCH] Converted mux4 to mux3 in dcache. --- wally-pipelined/src/cache/dcache.sv | 7 ++--- wally-pipelined/src/cache/dcachefsm.sv | 42 +++++++++++++------------- wally-pipelined/src/lsu/lsu.sv | 2 +- 3 files changed, 25 insertions(+), 26 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index ccfc7fa3a..1a41e7aa5 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -128,11 +128,10 @@ module dcache // Read Path CPU (IEU) side - mux4 #(INDEXLEN) + mux3 #(INDEXLEN) AdrSelMux(.d0(MemAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), - .d1(7'b0), // *** REMOVE - .d2(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), - .d3(FlushAdr), + .d1(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), + .d2(FlushAdr), .s(SelAdrM), .y(RAdr)); diff --git a/wally-pipelined/src/cache/dcachefsm.sv b/wally-pipelined/src/cache/dcachefsm.sv index 35df55281..09594ce4d 100644 --- a/wally-pipelined/src/cache/dcachefsm.sv +++ b/wally-pipelined/src/cache/dcachefsm.sv @@ -150,19 +150,19 @@ module dcachefsm else if(FlushDCacheM) begin NextState = STATE_FLUSH; DCacheStall = 1'b1; - SelAdrM = 2'b11; + SelAdrM = 2'b10; FlushAdrCntRst = 1'b1; FlushWayCntRst = 1'b1; end // amo hit else if(AtomicM[1] & (&MemRWM) & CacheableM & CacheHit) begin - SelAdrM = 2'b10; + SelAdrM = 2'b01; DCacheStall = 1'b0; if(CPUBusy) begin NextState = STATE_CPU_BUSY_FINISH_AMO; - SelAdrM = 2'b10; + SelAdrM = 2'b01; end else begin SRAMWordWriteEnableM = 1'b1; @@ -178,7 +178,7 @@ module dcachefsm if(CPUBusy) begin NextState = STATE_CPU_BUSY; - SelAdrM = 2'b10; + SelAdrM = 2'b01; end else begin NextState = STATE_READY; @@ -186,7 +186,7 @@ module dcachefsm end // write hit valid cached else if (MemRWM[0] & CacheableM & CacheHit) begin - SelAdrM = 2'b10; + SelAdrM = 2'b01; DCacheStall = 1'b0; SRAMWordWriteEnableM = 1'b1; SetDirty = 1'b1; @@ -194,7 +194,7 @@ module dcachefsm if(CPUBusy) begin NextState = STATE_CPU_BUSY; - SelAdrM = 2'b10; + SelAdrM = 2'b01; end else begin NextState = STATE_READY; @@ -211,7 +211,7 @@ module dcachefsm STATE_MISS_FETCH_WDV: begin DCacheStall = 1'b1; - SelAdrM = 2'b10; + SelAdrM = 2'b01; if (BUSACK) begin NextState = STATE_MISS_FETCH_DONE; @@ -222,7 +222,7 @@ module dcachefsm STATE_MISS_FETCH_DONE: begin DCacheStall = 1'b1; - SelAdrM = 2'b10; + SelAdrM = 2'b01; if(VictimDirty) begin NextState = STATE_MISS_EVICT_DIRTY; DCWriteLine = 1'b1; @@ -235,14 +235,14 @@ module dcachefsm SRAMBlockWriteEnableM = 1'b1; DCacheStall = 1'b1; NextState = STATE_MISS_READ_WORD; - SelAdrM = 2'b10; + SelAdrM = 2'b01; SetValid = 1'b1; ClearDirty = 1'b1; //LRUWriteEn = 1'b1; // DO not update LRU on SRAM fetch update. Wait for subsequent read/write end STATE_MISS_READ_WORD: begin - SelAdrM = 2'b10; + SelAdrM = 2'b01; DCacheStall = 1'b1; if (MemRWM[0] & ~AtomicM[1]) begin // handles stores and amo write. NextState = STATE_MISS_WRITE_WORD; @@ -254,12 +254,12 @@ module dcachefsm end STATE_MISS_READ_WORD_DELAY: begin - //SelAdrM = 2'b10; + //SelAdrM = 2'b01; SRAMWordWriteEnableM = 1'b0; SetDirty = 1'b0; LRUWriteEn = 1'b0; if(&MemRWM & AtomicM[1]) begin // amo write - SelAdrM = 2'b10; + SelAdrM = 2'b01; if(CPUBusy) begin NextState = STATE_CPU_BUSY_FINISH_AMO; end @@ -273,7 +273,7 @@ module dcachefsm LRUWriteEn = 1'b1; if(CPUBusy) begin NextState = STATE_CPU_BUSY; - SelAdrM = 2'b10; + SelAdrM = 2'b01; end else begin NextState = STATE_READY; @@ -284,11 +284,11 @@ module dcachefsm STATE_MISS_WRITE_WORD: begin SRAMWordWriteEnableM = 1'b1; SetDirty = 1'b1; - SelAdrM = 2'b10; + SelAdrM = 2'b01; LRUWriteEn = 1'b1; if(CPUBusy) begin NextState = STATE_CPU_BUSY; - SelAdrM = 2'b10; + SelAdrM = 2'b01; end else begin NextState = STATE_READY; @@ -297,7 +297,7 @@ module dcachefsm STATE_MISS_EVICT_DIRTY: begin DCacheStall = 1'b1; - SelAdrM = 2'b10; + SelAdrM = 2'b01; SelEvict = 1'b1; if(BUSACK) begin NextState = STATE_MISS_WRITE_CACHE_BLOCK; @@ -311,7 +311,7 @@ module dcachefsm SelAdrM = 2'b00; if(CPUBusy) begin NextState = STATE_CPU_BUSY; - SelAdrM = 2'b10; + SelAdrM = 2'b01; end else begin NextState = STATE_READY; @@ -319,7 +319,7 @@ module dcachefsm end STATE_CPU_BUSY_FINISH_AMO: begin - SelAdrM = 2'b10; + SelAdrM = 2'b01; SRAMWordWriteEnableM = 1'b0; SetDirty = 1'b0; LRUWriteEn = 1'b0; @@ -336,7 +336,7 @@ module dcachefsm STATE_FLUSH: begin DCacheStall = 1'b1; - SelAdrM = 2'b11; + SelAdrM = 2'b10; SelFlush = 1'b1; FlushAdrCntEn = 1'b1; FlushWayCntEn = 1'b1; @@ -357,7 +357,7 @@ module dcachefsm STATE_FLUSH_WRITE_BACK: begin DCacheStall = 1'b1; - SelAdrM = 2'b11; + SelAdrM = 2'b10; SelFlush = 1'b1; if(BUSACK) begin NextState = STATE_FLUSH_CLEAR_DIRTY; @@ -371,7 +371,7 @@ module dcachefsm ClearDirty = 1'b1; VDWriteEnable = 1'b1; SelFlush = 1'b1; - SelAdrM = 2'b11; + SelAdrM = 2'b10; FlushAdrCntEn = 1'b0; FlushWayCntEn = 1'b0; if(FlushAdrFlag) begin diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index d325f1ad5..248793141 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -488,7 +488,7 @@ module lsu STATE_BUS_UNCACHED_READ_DONE: if(CPUBusy) BusNextState = STATE_BUS_CPU_BUSY; else BusNextState = STATE_BUS_READY; STATE_BUS_CPU_BUSY: if(CPUBusy) BusNextState = STATE_BUS_CPU_BUSY; - else BusNextState = STATE_BUS_READY; + else BusNextState = STATE_BUS_READY; STATE_BUS_FETCH: if (WordCountFlag & LsuBusAck) BusNextState = STATE_BUS_READY; else BusNextState = STATE_BUS_FETCH; STATE_BUS_WRITE: if(WordCountFlag & LsuBusAck) BusNextState = STATE_BUS_READY;