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Simplify macro

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Jordan Carlin 2025-01-29 18:53:11 -08:00
parent a06a91f7a5
commit fdfef5a490
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1 changed files with 4 additions and 9 deletions
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13
testbench/common/wallyTracer.sv
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@ -21,7 +21,6 @@
// and limitations under the License. // and limitations under the License.
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
`define STD_LOG 0 `define STD_LOG 0
`define PRINT_PC_INSTR 0 `define PRINT_PC_INSTR 0
`define PRINT_MOST 0 `define PRINT_MOST 0
@ -30,16 +29,12 @@
// Since we are detecting the CSR change by comparing the old value, we need to // Since we are detecting the CSR change by comparing the old value, we need to
// ensure the CSR is detected when the pipeline's Writeback stage is not // ensure the CSR is detected when the pipeline's Writeback stage is not
// stalled. If it is stalled we want CSRArray to hold the old value. // stalled. If it is stalled we want to hold the old value.
`define CONNECT_CSR(addr, val) \ `define CONNECT_CSR(addr, val) \
always_comb \
if (valid) CSRArray[addr] = val; \
else CSRArray[addr] = CSRArrayOld[addr]; \
always_ff @(posedge clk) \ always_ff @(posedge clk) \
CSRArrayOld[addr] = CSRArray[addr]; \ CSRArrayOld[addr] = rvvi.csr[0][0][addr]; \
assign CSR_W[addr] = (CSRArrayOld[addr] != CSRArray[addr]) ? 1 : 0; \ assign rvvi.csr_wb[0][0][addr] = (rvvi.csr[0][0][addr] != CSRArrayOld[addr]); \
assign rvvi.csr_wb[0][0][addr] = CSR_W[addr]; \ assign rvvi.csr[0][0][addr] = valid ? val : CSRArrayOld[addr];
assign rvvi.csr[0][0][addr] = CSRArray[addr];
module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);