Clean up some stuff

wally-pipelined/src/ebu/ahblite.sv

@@ -71,7 +71,7 @@ module ahblite (
   output logic [3:0]       HSIZED,
   output logic             HWRITED,
   // Stalls
-  output logic             InstrStall,/*InstrUpdate, */DataStall
+  output logic             /*InstrUpdate, */DataStall
   // *** add a chip-level ready signal as part of handshake
 );
 
@@ -135,8 +135,7 @@ module ahblite (
 
   // stall signals
   assign #2 DataStall = (NextBusState == MEMREAD) || (NextBusState == MEMWRITE) || 
-                        (NextBusState == ATOMICREAD) || (NextBusState == ATOMICWRITE) ||
+                        (NextBusState == ATOMICREAD) || (NextBusState == ATOMICWRITE);
-                        (NextBusState == MMUTRANSLATE) || (NextBusState == MMUIDLE);
   // *** Could get finer grained stalling if we distinguish between MMU
   //     instruction address translation and data address translation
   assign #1 InstrStall = (NextBusState == INSTRREAD) || (NextBusState == INSTRREADC) ||

wally-pipelined/src/hazard/hazard.sv

@@ -29,7 +29,7 @@ module hazard(
   // Detect hazards
   input  logic       BPPredWrongE, CSRWritePendingDEM, RetM, TrapM,
   input  logic       LoadStallD, MulDivStallD, CSRRdStallD,
-  input  logic       InstrStall, DataStall, ICacheStallF,
+  input  logic       DataStall, ICacheStallF,
   // Stall & flush outputs
   output logic       StallF, StallD, StallE, StallM, StallW,
   output logic       FlushF, FlushD, FlushE, FlushM, FlushW

wally-pipelined/src/wally/wallypipelinedhart.sv

@@ -111,7 +111,7 @@ module wallypipelinedhart (
   logic [`XLEN-1:0] InstrPAdrF;
   logic [`XLEN-1:0] InstrRData;
   logic             InstrReadF;
-  logic             DataStall, InstrStall;
+  logic             DataStall;
   logic             InstrAckF, MemAckW;
 
   logic             BPPredWrongE, BPPredWrongM;