diff --git a/src/privileged/csrc.sv b/src/privileged/csrc.sv
index ad9475d32..d61835826 100644
--- a/src/privileged/csrc.sv
+++ b/src/privileged/csrc.sv
@@ -94,9 +94,9 @@ module csrc #(parameter
     assign CounterEvent[9] = InstrClassM[2] & InstrValidNotFlushedM;                    // return instructions
     assign CounterEvent[10] = PredictionInstrClassWrongM & InstrValidNotFlushedM;       // instruction class predictor wrong
     assign CounterEvent[11] = DCacheAccess & InstrValidNotFlushedM;                     // data cache access
-    assign CounterEvent[12] = DCacheMiss & InstrValidNotFlushedM;                       // data cache miss
+    assign CounterEvent[12] = DCacheMiss;                                               // data cache miss. Miss asserted 1 cycle at start of cache miss
     assign CounterEvent[13] = ICacheAccess & InstrValidNotFlushedM;                     // instruction cache access
-    assign CounterEvent[14] = ICacheMiss & InstrValidNotFlushedM;                       // instruction cache miss
+    assign CounterEvent[14] = ICacheMiss;                                               // instruction cache miss. Miss asserted 1 cycle at start of cache miss
 	assign CounterEvent[15] = BPPredWrongM & InstrValidNotFlushedM;                     // branch predictor wrong
     assign CounterEvent[`COUNTERS-1:16] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions
   end