Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Privileged unit formatting

Browse Source
This commit is contained in:
David Harris 2023-01-12 07:41:30 -08:00
parent e58879f2d0
commit fdcb1f08ce
1 changed files with 34 additions and 55 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

89
pipelined/src/privileged/privileged.sv
View File

@ -30,7 +30,8 @@
// *** remove signals not needed by PMA/PMP now that it is moved // *** remove signals not needed by PMA/PMP now that it is moved
module privileged ( module privileged (
input logic clk, reset, input logic clk, reset,
input logic FlushD, FlushE, FlushM, FlushW, StallD, StallE, StallM, StallW, input logic StallD, StallE, StallM, StallW,
input logic FlushD, FlushE, FlushM, FlushW,
(* mark_debug = "true" *) input logic CSRReadM, CSRWriteM, (* mark_debug = "true" *) input logic CSRReadM, CSRWriteM,
input logic [`XLEN-1:0] SrcAM, input logic [`XLEN-1:0] SrcAM,
input logic [`XLEN-1:0] PCM, PCNext2F, input logic [`XLEN-1:0] PCM, PCNext2F,
@ -44,7 +45,7 @@ module privileged (
input logic DirPredictionWrongM, input logic DirPredictionWrongM,
input logic BTBPredPCWrongM, input logic BTBPredPCWrongM,
input logic RASPredPCWrongM, input logic RASPredPCWrongM,
input logic PredictionInstrClassWrongM, input logic PredictionInstrClassWrongM,
input logic [4:0] InstrClassM, input logic [4:0] InstrClassM,
input logic DCacheMiss, input logic DCacheMiss,
input logic DCacheAccess, input logic DCacheAccess,
@ -101,69 +102,47 @@ module privileged (
logic DelegateM; logic DelegateM;
logic wfiM, IntPendingM; logic wfiM, IntPendingM;
///////////////////////////////////////////
// track the current privilege level // track the current privilege level
///////////////////////////////////////////
privmode privmode(.clk, .reset, .StallW, .TrapM, .mretM, .sretM, .DelegateM, privmode privmode(.clk, .reset, .StallW, .TrapM, .mretM, .sretM, .DelegateM,
.STATUS_MPP, .STATUS_SPP, .NextPrivilegeModeM, .PrivilegeModeW); .STATUS_MPP, .STATUS_SPP, .NextPrivilegeModeM, .PrivilegeModeW);
///////////////////////////////////////////
// decode privileged instructions // decode privileged instructions
/////////////////////////////////////////// privdec pmd(.clk, .reset, .StallM, .InstrM(InstrM[31:20]),
.PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM,
.PrivilegeModeW, .STATUS_TSR, .STATUS_TVM, .STATUS_TW, .IllegalInstrFaultM,
.EcallFaultM, .BreakpointFaultM, .sretM, .mretM, .wfiM, .sfencevmaM);
privdec pmd(.clk, .reset, .StallM, .InstrM(InstrM[31:20]),
.PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM,
.PrivilegeModeW, .STATUS_TSR, .STATUS_TVM, .STATUS_TW, .IllegalInstrFaultM,
.EcallFaultM, .BreakpointFaultM,
.sretM, .mretM, .wfiM, .sfencevmaM);
///////////////////////////////////////////
// Control and Status Registers // Control and Status Registers
/////////////////////////////////////////// csr csr(.clk, .reset, .FlushM, .FlushW, .StallE, .StallM, .StallW,
csr csr(.clk, .reset, .InstrM, .PCM, .SrcAM, .IEUAdrM, .PCNext2F,
.FlushM, .FlushW, .CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .wfiM, .IntPendingM, .InterruptM,
.StallE, .StallM, .StallW, .MTimerInt, .MExtInt, .SExtInt, .MSwInt,
.InstrM, .PCM, .SrcAM, .IEUAdrM, .PCNext2F, .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD,
.CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .wfiM, .IntPendingM, .InterruptM, .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM,
.MTimerInt, .MExtInt, .SExtInt, .MSwInt, .PredictionInstrClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
.MTIME_CLINT, .NextPrivilegeModeM, .PrivilegeModeW, .CauseM, .SelHPTW,
.InstrValidM, .FRegWriteM, .LoadStallD, .STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TVM,
.DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TW, .STATUS_FS,
.PredictionInstrClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .MEDELEG_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW,
.NextPrivilegeModeM, .PrivilegeModeW, .SATP_REGW, .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
.CauseM, .SelHPTW, .SetFflagsM, .FRM_REGW,
.STATUS_MPP, .CSRReadValW,.UnalignedPCNextF, .IllegalCSRAccessM, .BigEndianM);
.STATUS_SPP, .STATUS_TSR, .STATUS_TVM,
.MEDELEG_REGW,
.SATP_REGW,
.MIP_REGW, .MIE_REGW, .MIDELEG_REGW,
.STATUS_MIE, .STATUS_SIE,
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TW, .STATUS_FS,
.PMPCFG_ARRAY_REGW,
.PMPADDR_ARRAY_REGW,
.SetFflagsM,
.FRM_REGW,
.CSRReadValW,.UnalignedPCNextF,
.IllegalCSRAccessM, .BigEndianM);
// pipeline early-arriving trap sources
privpiperegs ppr(.clk, .reset, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, privpiperegs ppr(.clk, .reset, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
.InstrPageFaultF, .InstrAccessFaultF, .IllegalIEUInstrFaultD, .InstrPageFaultF, .InstrAccessFaultF, .IllegalIEUInstrFaultD,
.InstrPageFaultM, .InstrAccessFaultM, .IllegalIEUInstrFaultM); .InstrPageFaultM, .InstrAccessFaultM, .IllegalIEUInstrFaultM);
// trap logic
trap trap(.reset, trap trap(.reset,
.InstrMisalignedFaultM, .InstrAccessFaultM, .HPTWInstrAccessFaultM, .IllegalInstrFaultM, .InstrMisalignedFaultM, .InstrAccessFaultM, .HPTWInstrAccessFaultM, .IllegalInstrFaultM,
.BreakpointFaultM, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM, .BreakpointFaultM, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
.LoadAccessFaultM, .StoreAmoAccessFaultM, .EcallFaultM, .InstrPageFaultM, .LoadAccessFaultM, .StoreAmoAccessFaultM, .EcallFaultM, .InstrPageFaultM,
.LoadPageFaultM, .StoreAmoPageFaultM, .LoadPageFaultM, .StoreAmoPageFaultM,
.mretM, .sretM, .mretM, .sretM, .PrivilegeModeW,
.PrivilegeModeW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .MEDELEG_REGW, .STATUS_MIE, .STATUS_SIE,
.MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .MEDELEG_REGW, .InstrValidM, .CommittedM, .CommittedF,
.STATUS_MIE, .STATUS_SIE, .TrapM, .RetM, .wfiM, .InterruptM, .IntPendingM, .DelegateM, .WFIStallM, .CauseM);
.InstrValidM, .CommittedM, .CommittedF,
.TrapM, .RetM, .wfiM,
.InterruptM, .IntPendingM, .DelegateM, .WFIStallM,
.CauseM);
endmodule endmodule