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Privileged unit formatting

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This commit is contained in:
David Harris 2023-01-12 07:41:30 -08:00
parent e58879f2d0
commit fdcb1f08ce
1 changed files with 34 additions and 55 deletions
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55
pipelined/src/privileged/privileged.sv
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@ -30,7 +30,8 @@
// *** remove signals not needed by PMA/PMP now that it is moved // *** remove signals not needed by PMA/PMP now that it is moved
module privileged ( module privileged (
input logic clk, reset, input logic clk, reset,
input logic FlushD, FlushE, FlushM, FlushW, StallD, StallE, StallM, StallW, input logic StallD, StallE, StallM, StallW,
input logic FlushD, FlushE, FlushM, FlushW,
(* mark_debug = "true" *) input logic CSRReadM, CSRWriteM, (* mark_debug = "true" *) input logic CSRReadM, CSRWriteM,
input logic [`XLEN-1:0] SrcAM, input logic [`XLEN-1:0] SrcAM,
input logic [`XLEN-1:0] PCM, PCNext2F, input logic [`XLEN-1:0] PCM, PCNext2F,
@ -101,69 +102,47 @@ module privileged (
logic DelegateM; logic DelegateM;
logic wfiM, IntPendingM; logic wfiM, IntPendingM;
///////////////////////////////////////////
// track the current privilege level // track the current privilege level
///////////////////////////////////////////
privmode privmode(.clk, .reset, .StallW, .TrapM, .mretM, .sretM, .DelegateM, privmode privmode(.clk, .reset, .StallW, .TrapM, .mretM, .sretM, .DelegateM,
.STATUS_MPP, .STATUS_SPP, .NextPrivilegeModeM, .PrivilegeModeW); .STATUS_MPP, .STATUS_SPP, .NextPrivilegeModeM, .PrivilegeModeW);
///////////////////////////////////////////
// decode privileged instructions // decode privileged instructions
///////////////////////////////////////////
privdec pmd(.clk, .reset, .StallM, .InstrM(InstrM[31:20]), privdec pmd(.clk, .reset, .StallM, .InstrM(InstrM[31:20]),
.PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM, .PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM,
.PrivilegeModeW, .STATUS_TSR, .STATUS_TVM, .STATUS_TW, .IllegalInstrFaultM, .PrivilegeModeW, .STATUS_TSR, .STATUS_TVM, .STATUS_TW, .IllegalInstrFaultM,
.EcallFaultM, .BreakpointFaultM, .EcallFaultM, .BreakpointFaultM, .sretM, .mretM, .wfiM, .sfencevmaM);
.sretM, .mretM, .wfiM, .sfencevmaM);
///////////////////////////////////////////
// Control and Status Registers // Control and Status Registers
/////////////////////////////////////////// csr csr(.clk, .reset, .FlushM, .FlushW, .StallE, .StallM, .StallW,
csr csr(.clk, .reset,
.FlushM, .FlushW,
.StallE, .StallM, .StallW,
.InstrM, .PCM, .SrcAM, .IEUAdrM, .PCNext2F, .InstrM, .PCM, .SrcAM, .IEUAdrM, .PCNext2F,
.CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .wfiM, .IntPendingM, .InterruptM, .CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .wfiM, .IntPendingM, .InterruptM,
.MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTimerInt, .MExtInt, .SExtInt, .MSwInt,
.MTIME_CLINT, .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD,
.InstrValidM, .FRegWriteM, .LoadStallD,
.DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM,
.PredictionInstrClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PredictionInstrClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
.NextPrivilegeModeM, .PrivilegeModeW, .NextPrivilegeModeM, .PrivilegeModeW, .CauseM, .SelHPTW,
.CauseM, .SelHPTW, .STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TVM,
.STATUS_MPP, .STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TW, .STATUS_FS,
.STATUS_SPP, .STATUS_TSR, .STATUS_TVM, .MEDELEG_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW,
.MEDELEG_REGW, .SATP_REGW, .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
.SATP_REGW, .SetFflagsM, .FRM_REGW,
.MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .CSRReadValW,.UnalignedPCNextF, .IllegalCSRAccessM, .BigEndianM);
.STATUS_MIE, .STATUS_SIE,
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TW, .STATUS_FS,
.PMPCFG_ARRAY_REGW,
.PMPADDR_ARRAY_REGW,
.SetFflagsM,
.FRM_REGW,
.CSRReadValW,.UnalignedPCNextF,
.IllegalCSRAccessM, .BigEndianM);
// pipeline early-arriving trap sources
privpiperegs ppr(.clk, .reset, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, privpiperegs ppr(.clk, .reset, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
.InstrPageFaultF, .InstrAccessFaultF, .IllegalIEUInstrFaultD, .InstrPageFaultF, .InstrAccessFaultF, .IllegalIEUInstrFaultD,
.InstrPageFaultM, .InstrAccessFaultM, .IllegalIEUInstrFaultM); .InstrPageFaultM, .InstrAccessFaultM, .IllegalIEUInstrFaultM);
// trap logic
trap trap(.reset, trap trap(.reset,
.InstrMisalignedFaultM, .InstrAccessFaultM, .HPTWInstrAccessFaultM, .IllegalInstrFaultM, .InstrMisalignedFaultM, .InstrAccessFaultM, .HPTWInstrAccessFaultM, .IllegalInstrFaultM,
.BreakpointFaultM, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM, .BreakpointFaultM, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
.LoadAccessFaultM, .StoreAmoAccessFaultM, .EcallFaultM, .InstrPageFaultM, .LoadAccessFaultM, .StoreAmoAccessFaultM, .EcallFaultM, .InstrPageFaultM,
.LoadPageFaultM, .StoreAmoPageFaultM, .LoadPageFaultM, .StoreAmoPageFaultM,
.mretM, .sretM, .mretM, .sretM, .PrivilegeModeW,
.PrivilegeModeW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .MEDELEG_REGW, .STATUS_MIE, .STATUS_SIE,
.MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .MEDELEG_REGW,
.STATUS_MIE, .STATUS_SIE,
.InstrValidM, .CommittedM, .CommittedF, .InstrValidM, .CommittedM, .CommittedF,
.TrapM, .RetM, .wfiM, .TrapM, .RetM, .wfiM, .InterruptM, .IntPendingM, .DelegateM, .WFIStallM, .CauseM);
.InterruptM, .IntPendingM, .DelegateM, .WFIStallM,
.CauseM);
endmodule endmodule