diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv
index c43c3ec25..bc867bd85 100644
--- a/wally-pipelined/src/ifu/ifu.sv
+++ b/wally-pipelined/src/ifu/ifu.sv
@@ -61,7 +61,7 @@ module ifu (
   input logic  [1:0]       PrivilegeModeW,
   input logic  [`XLEN-1:0] PageTableEntryF,
   input logic  [`XLEN-1:0] SATP_REGW,
-  input logic              ITLBWriteF, // ITLBFlushF,
+  input logic              ITLBWriteF, ITLBFlushF,
   output logic             ITLBMissF, ITLBHitF
 );
 
@@ -75,11 +75,6 @@ module ifu (
   logic [31:0]      nop = 32'h00000013; // instruction for NOP
   logic [`XLEN-1:0] ITLBInstrPAdrF, ICacheInstrPAdrF;
 
-  // *** temporary hack until walker is hooked up -- Thomas F
-  // logic  [`XLEN-1:0] PageTableEntryF = '0;
-  logic ITLBFlushF = '0;
-  // logic ITLBWriteF = '0;
-
   tlb #(3) itlb(clk, reset, SATP_REGW, PrivilegeModeW, 1'b1, PCF, PageTableEntryF, ITLBWriteF, ITLBFlushF,
     ITLBInstrPAdrF, ITLBMissF, ITLBHitF);
 
diff --git a/wally-pipelined/src/mmu/tlb.sv b/wally-pipelined/src/mmu/tlb.sv
index 4fb1b6fe5..8b84a9929 100644
--- a/wally-pipelined/src/mmu/tlb.sv
+++ b/wally-pipelined/src/mmu/tlb.sv
@@ -126,9 +126,6 @@ module tlb #(parameter ENTRY_BITS = 3) (
   assign VirtualPageNumber = VirtualAddress[`VPN_BITS+11:12];
   assign PageOffset        = VirtualAddress[11:0];
 
-  // Choose a read or write location to the entry list
-  mux2 #(3) indexmux(VPNIndex, WriteIndex, TLBWrite, EntryIndex);
-
   // Currently use random replacement algorithm
   tlb_rand rdm(.*);
 
@@ -160,7 +157,8 @@ endmodule
 
 module tlb_ram #(parameter ENTRY_BITS = 3) (
   input                   clk, reset,
-  input  [ENTRY_BITS-1:0] EntryIndex,
+  input  [ENTRY_BITS-1:0] VPNIndex,  // Index to read from
+  input  [ENTRY_BITS-1:0] WriteIndex,
   input  [`XLEN-1:0]      PageTableEntryWrite,
   input                   TLBWrite,
 
@@ -171,10 +169,10 @@ module tlb_ram #(parameter ENTRY_BITS = 3) (
 
   logic [`XLEN-1:0] ram [0:NENTRIES-1];
   always @(posedge clk) begin
-    if (TLBWrite) ram[EntryIndex] <= PageTableEntryWrite;
+    if (TLBWrite) ram[WriteIndex] <= PageTableEntryWrite;
   end
 
-  assign PageTableEntry = ram[EntryIndex];
+  assign PageTableEntry = ram[VPNIndex];
     
   initial begin
     for (int i = 0; i < NENTRIES; i++)
diff --git a/wally-pipelined/src/privileged/csrs.sv b/wally-pipelined/src/privileged/csrs.sv
index ede8274a7..7f08d95a6 100644
--- a/wally-pipelined/src/privileged/csrs.sv
+++ b/wally-pipelined/src/privileged/csrs.sv
@@ -72,7 +72,7 @@ module csrs #(parameter
       assign WriteSEPCM = STrapM | (CSRSWriteM && (CSRAdrM == SEPC));
       assign WriteSCAUSEM = STrapM | (CSRSWriteM && (CSRAdrM == SCAUSE));
       assign WriteSTVALM = STrapM | (CSRSWriteM && (CSRAdrM == STVAL));
-      assign WriteSATPM = STrapM | (CSRSWriteM && (CSRAdrM == SATP));
+      assign WriteSATPM = CSRSWriteM && (CSRAdrM == SATP);
       assign WriteSCOUNTERENM = CSRSWriteM && (CSRAdrM == SCOUNTEREN);
 
       // CSRs
diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv
index 16a3d5db0..4d772dc20 100644
--- a/wally-pipelined/src/privileged/privileged.sv
+++ b/wally-pipelined/src/privileged/privileged.sv
@@ -36,6 +36,7 @@ module privileged (
   output logic [`XLEN-1:0] CSRReadValW,
   output logic [`XLEN-1:0] PrivilegedNextPCM,
   output logic             RetM, TrapM,
+  output logic             ITLBFlushF, DTLBFlushM,
   input  logic             InstrValidW, FloatRegWriteW, LoadStallD, BPPredWrongM,
   input  logic [3:0]       InstrClassM,
   input  logic             PrivilegedM,
@@ -119,6 +120,8 @@ module privileged (
 
   assign BreakpointFaultM = ebreakM; // could have other causes too
   assign EcallFaultM = ecallM;
+  assign ITLBFlushF = sfencevmaM;
+  assign DTLBFlushM = sfencevmaM;
   // *** Page faults now driven by page table walker. Might need to make the
   // below signals ORs of a walker fault and a tlb fault if both of those come in
   // assign InstrPageFaultM = 0;
diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv
index 72619cdd3..b3447d3e1 100644
--- a/wally-pipelined/src/wally/wallypipelinedhart.sv
+++ b/wally-pipelined/src/wally/wallypipelinedhart.sv
@@ -92,6 +92,7 @@ module wallypipelinedhart (
 
   // memory management unit signals
   logic             ITLBWriteF, DTLBWriteM;
+  logic             ITLBFlushF, DTLBFlushM;
   logic             ITLBMissF, ITLBHitF;
   logic             DTLBMissM, DTLBHitM;
   logic [`XLEN-1:0] SATP_REGW;
diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv
index fd1184603..53e332206 100644
--- a/wally-pipelined/testbench/testbench-imperas.sv
+++ b/wally-pipelined/testbench/testbench-imperas.sv
@@ -367,7 +367,7 @@ string tests32i[] = {
         // if (`F_SUPPORTED) tests = {tests64f, tests};
         // if (`D_SUPPORTED) tests = {tests64d, tests};
         if (`A_SUPPORTED) tests = {tests, tests64a};
-        if (`MEM_VIRTMEM) tests = {tests, tests64mmu};
+        //if (`MEM_VIRTMEM) tests = {tests, tests64mmu};
       end
  //     tests = {tests64a, tests};
       tests = {tests, tests64p};