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No dcache now supported. Does not pass regression tests however.

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This commit is contained in:
Ross Thompson 2021-12-30 15:26:32 -06:00
parent bd531d1996
commit fd77022f73
2 changed files with 61 additions and 55 deletions
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4
wally-pipelined/src/lsu/lsu.sv
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@ -274,8 +274,8 @@ module lsu
// 2. cache `MEM_DCACHE
// 3. wire pass-through
localparam integer WORDSPERLINE = `MEM_DCACHE ? `DCACHE_BLOCKLENINBITS/`XLEN : `XLEN/8;
localparam integer LOGWPL = $clog2(WORDSPERLINE);
localparam integer WORDSPERLINE = `MEM_DCACHE ? `DCACHE_BLOCKLENINBITS/`XLEN : 1;
localparam integer LOGWPL = `MEM_DCACHE ? $clog2(WORDSPERLINE) : 1;
localparam integer BLOCKLEN = `MEM_DCACHE ? `DCACHE_BLOCKLENINBITS : `XLEN;
localparam integer WordCountThreshold = `MEM_DCACHE ? WORDSPERLINE - 1 : 0;

18
wally-pipelined/testbench/testbench.sv
View File

@ -365,6 +365,12 @@ module DCacheFlushFSM
input logic start,
output logic done);
genvar adr;
logic [`XLEN-1:0] ShadowRAM[`RAM_BASE>>(1+`XLEN/32):(`RAM_RANGE+`RAM_BASE)>>1+(`XLEN/32)];
generate
if(`MEM_DCACHE) begin
localparam integer numlines = testbench.dut.hart.lsu.dcache.dcache.NUMLINES;
localparam integer numways = testbench.dut.hart.lsu.dcache.dcache.NUMWAYS;
localparam integer blockbytelen = testbench.dut.hart.lsu.dcache.dcache.BLOCKBYTELEN;
@ -382,11 +388,6 @@ module DCacheFlushFSM
logic CacheValid [numways-1:0] [numlines-1:0] [numwords-1:0];
logic CacheDirty [numways-1:0] [numlines-1:0] [numwords-1:0];
logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [numwords-1:0];
genvar adr;
logic [`XLEN-1:0] ShadowRAM[`RAM_BASE>>(1+`XLEN/32):(`RAM_RANGE+`RAM_BASE)>>1+(`XLEN/32)];
generate
for(index = 0; index < numlines; index++) begin
for(way = 0; way < numways; way++) begin
for(cacheWord = 0; cacheWord < numwords; cacheWord++) begin
@ -408,7 +409,6 @@ module DCacheFlushFSM
end
end
end
endgenerate
integer i, j, k;
@ -428,6 +428,12 @@ module DCacheFlushFSM
end
end
endgenerate
flop #(1) doneReg(.clk(clk),
.d(start),
.q(done));