From fd6a6b224959bc29f131558695945aee88d97579 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 20 Apr 2024 22:52:08 -0700 Subject: [PATCH] environment variable cleanup --- config/shared/config-shared.vh | 11 +++++++--- sim/vcs/run_vcs | 6 ++++-- src/generic/flop/flopens.sv | 38 ---------------------------------- src/generic/mem/rom1p1r.sv | 17 ++++----------- testbench/testbench.sv | 18 +++++----------- 5 files changed, 21 insertions(+), 69 deletions(-) delete mode 100644 src/generic/flop/flopens.sv diff --git a/config/shared/config-shared.vh b/config/shared/config-shared.vh index 3c316958d..db2a62377 100644 --- a/config/shared/config-shared.vh +++ b/config/shared/config-shared.vh @@ -131,7 +131,12 @@ localparam CORRSHIFTSZ = NORMSHIFTSZ-2; // Drop lead /* verilator lint_off PINCONNECTEMPTY */ `ifdef VERILATOR -import "DPI-C" function string getenvval(input string env_name); + import "DPI-C" function string getenvval(input string env_name); + string RISCV_DIR = getenvval("RISCV"); // "/opt/riscv"; + string WALLY_DIR = getenvval("WALLY"); `else -import "DPI-C" function string getenv(input string env_name); -`endif \ No newline at end of file +// import "DPI-C" function string getenv(input string env_name); +// string RISCV_DIR = getenv("RISCV"); // "/opt/riscv"; + string RISCV_DIR = "$RISCV"; // "/opt/riscv"; + string WALLY_DIR = "$WALLY"; +`endif diff --git a/sim/vcs/run_vcs b/sim/vcs/run_vcs index a78939ac4..cde1c50d7 100755 --- a/sim/vcs/run_vcs +++ b/sim/vcs/run_vcs @@ -1,6 +1,7 @@ #!/bin/bash # VCS Compilation for WALLY # Divya Kohli, Rose Thompson, David Harris 2024 +# Note: VCS produces warning about unsupported Linux Version, but runs successfully # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 CFG=${WALLY}/config @@ -27,7 +28,8 @@ clean() { # Clean and run simulation with VCS clean #vcs +lint=all,noGCWM -simprofile -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse -v2k_generate ${SOURCE_PATH} +define+TEST=$TESTSUITE $SIMFILES -o $OUTPUT -error=NOODV -# lint ignores Unused Inputs (UI), Unnamed Assertipons (SVA-UA), Dynamic Type Sensitivty [IDTS] -vcs +lint=all,noGCWM,noUI,noSVA-UA,noIDTS -simprofile -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse -v2k_generate ${SOURCE_PATH} -pvalue+testbench.TEST=$TESTSUITE $SIMFILES -o $OUTPUT -error=NOODV +# lint ignores Unused Inputs (UI), Unnamed Assertipons (SVA-UA), Dynamic Type Sensitivty [IDTS], Null Statement [NS], Unequal Length in Comparison Operation [ULCO] +# ,noOBSV2G +vcs +lint=all,noGCWM,noUI,noSVA-UA,noIDTS,noNS,noULCO,noCAWM-L,noWMIA-L -simprofile -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse ${SOURCE_PATH} -pvalue+testbench.TEST=$TESTSUITE $SIMFILES -o $OUTPUT -error=NOODV ./$OUTPUT | tee program.out diff --git a/src/generic/flop/flopens.sv b/src/generic/flop/flopens.sv deleted file mode 100644 index d5969128c..000000000 --- a/src/generic/flop/flopens.sv +++ /dev/null @@ -1,38 +0,0 @@ -/////////////////////////////////////////// -// flopens.sv -// -// Written: David_Harris@hmc.edu 9 January 2021 -// Modified: -// -// Purpose: D flip-flop with enable, synchronous set -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -module flopens #(parameter WIDTH = 8) ( - input logic clk, set, en, - input logic [WIDTH-1:0] d, - output logic [WIDTH-1:0] q); - - always_ff @(posedge clk) - if (set) q <= 1; - else if (en) q <= d; -endmodule - - diff --git a/src/generic/mem/rom1p1r.sv b/src/generic/mem/rom1p1r.sv index 7a53c529e..832de8fd8 100644 --- a/src/generic/mem/rom1p1r.sv +++ b/src/generic/mem/rom1p1r.sv @@ -46,20 +46,11 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, PRELOAD_ENABLED = 0) end else begin */ - initial begin - if (PRELOAD_ENABLED) begin -`ifdef VERILATOR - $readmemh({getenvval("WALLY"), "/fpga/src/boot.mem"}, ROM, 0); -`else - $readmemh("$WALLY/fpga/src/boot.mem", ROM, 0); -`endif - end - end - - always_ff @ (posedge clk) begin + initial + if (PRELOAD_ENABLED) $readmemh({WALLY_DIR,"/fpga/src/boot.mem"}, ROM, 0); + + always_ff @ (posedge clk) if(ce) dout <= ROM[addr]; - end - // for FPGA, initialize with zero-stage bootloader /*if(PRELOAD_ENABLED) begin diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 41a183a8f..577897271 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -33,9 +33,7 @@ `include "idv/idv.svh" `endif -import cvw::*; - -module testbench; +module testbench import cvw::*; (); /* verilator lint_off WIDTHTRUNC */ /* verilator lint_off WIDTHEXPAND */ parameter DEBUG=0; @@ -59,12 +57,6 @@ module testbench; // Variables that can be overwritten with $value$plusargs at start of simulation string TEST; integer INSTR_LIMIT; -`ifdef VERILATOR - string RISCV_DIR = getenvval("RISCV"); // "/opt/riscv"; -`else - string RISCV_DIR = getenv("RISCV"); // "/opt/riscv"; -`endif - // string RISCV_DIR = "/opt/riscv"; // DUT signals logic [P.AHBW-1:0] HRDATAEXT; @@ -255,9 +247,9 @@ module testbench; assign ResetThreshold = 3'd5; initial begin - TestBenchReset = 1; + TestBenchReset = 1'b1; # 100; - TestBenchReset = 0; + TestBenchReset = 1'b0; end always_ff @(posedge clk) @@ -501,7 +493,7 @@ module testbench; always @(posedge clk) if (ResetMem) // program memory is sometimes reset (e.g. for CoreMark, which needs zeroed memory) for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1) - dut.uncoregen.uncore.ram.ram.memory.RAM[adrindex] = 0; + dut.uncoregen.uncore.ram.ram.memory.RAM[adrindex] = '0; //////////////////////////////////////////////////////////////////////////////// // Actual hardware @@ -546,7 +538,7 @@ module testbench; // generate clock to sequence tests always begin - clk = 1; # 5; clk = 0; # 5; + clk = 1'b1; # 5; clk = 1'b0; # 5; end /*