Clean up warnings from Questa

pipelined/regression/makefile-memfile

@@ -5,7 +5,8 @@ WALLYDIR:= $(ROOT)/tests/wally-riscv-arch-test
 # IMPERASDIR	:= $(ROOT)/tests/imperas-riscv-tests
 # ALLDIRS := $(ARCHDIR)/$(SUFFIX) $(WALLYDIR)/$(SUFFIX) $(IMPERASDIR)/$(SUFFIX)
 IMPERASDIR	:= $(ROOT)/tests/imperas-riscv-tests
-ALLDIRS := $(ARCHDIR)/$(SUFFIX) $(WALLYDIR)/$(SUFFIX) 
+#ALLDIRS := $(ARCHDIR)/$(SUFFIX) $(WALLYDIR)/$(SUFFIX) 
+ALLDIRS := $(ARCHDIR)/$(SUFFIX)
 
 ELFFILES	?= $(shell find $(ALLDIRS) -type f -regex ".*\.elf")
 OBJDUMPFILES	?= $(shell find $(ALLDIRS) -type f -regex ".*\.elf.objdump")

pipelined/src/mmu/hptw.sv

@@ -98,7 +98,6 @@ module hptw (
   logic [2:0]                 HPTWSize; // 32 or 64 bit access
 	(* mark_debug = "true" *) statetype WalkerState, NextWalkerState, InitialWalkerState;
 
-
   // map hptw access faults onto either the original LSU load/store fault or instruction access fault
   assign LoadAccessFaultM 		 = WalkerState == IDLE ? LSULoadAccessFaultM : (LSULoadAccessFaultM | LSUStoreAmoAccessFaultM) & DTLBWalk & MemRWM[1] & ~MemRWM[0];
   assign StoreAmoAccessFaultM	 = WalkerState == IDLE ? LSUStoreAmoAccessFaultM : (LSULoadAccessFaultM | LSUStoreAmoAccessFaultM) & DTLBWalk & MemRWM[0];

pipelined/src/mmu/mmu.sv

@@ -107,16 +107,10 @@ module mmu #(parameter TLB_ENTRIES = 8, IMMU = 0) (
     .Cacheable, .Idempotent, .SelTIM,
     .PMAInstrAccessFaultF, .PMALoadAccessFaultM, .PMAStoreAmoAccessFaultM);
  
-  if (`PMP_ENTRIES > 0) // instantiate PMP
   pmpchecker pmpchecker(.PhysicalAddress, .PrivilegeModeW,
     .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
     .ExecuteAccessF, .WriteAccessM, .ReadAccessM,
     .PMPInstrAccessFaultF, .PMPLoadAccessFaultM, .PMPStoreAmoAccessFaultM);
-  else begin
-    assign PMPInstrAccessFaultF = 0;
-    assign PMPLoadAccessFaultM = 0;
-    assign PMPStoreAmoAccessFaultM = 0;
-  end
 
   // Access faults
   // If TLB miss and translating we want to not have faults from the PMA and PMP checkers.

pipelined/src/mmu/pmpchecker.sv

@@ -49,6 +49,7 @@ module pmpchecker (
   output logic                     PMPStoreAmoAccessFaultM
 );
 
+  if (`PMP_ENTRIES > 0) begin
     // Bit i is high when the address falls in PMP region i
     logic                    EnforcePMP;
     logic [`PMP_ENTRIES-1:0] Match; // physical address matches one of the pmp ranges
@@ -73,4 +74,9 @@ module pmpchecker (
     assign PMPInstrAccessFaultF     = EnforcePMP & ExecuteAccessF & ~|(X & FirstMatch) ;
     assign PMPStoreAmoAccessFaultM  = EnforcePMP & WriteAccessM   & ~|(W & FirstMatch) ;
     assign PMPLoadAccessFaultM      = EnforcePMP & ReadAccessM    & ~|(R & FirstMatch) ;
+  end else begin
+    assign PMPInstrAccessFaultF     = 0;
+    assign PMPStoreAmoAccessFaultM  = 0;
+    assign PMPLoadAccessFaultM      = 0;
+  end
  endmodule

pipelined/src/mmu/tlbcontrol.sv

@@ -63,12 +63,8 @@ module tlbcontrol #(parameter ITLB = 0) (
   // Determine whether TLB is being used
   assign TLBAccess = ReadAccess | WriteAccess;
 
-  if (`XLEN==64) // Check whether upper bits of 64-bit virtual addressses are all equal
+  // Check that upper bits are legal (all 0s or all 1s)
   vm64check vm64check(.SATP_MODE, .VAdr, .SV39Mode, .UpperBitsUnequalPageFault);
-  else begin
-    assign SV39Mode = 0;
-    assign UpperBitsUnequalPageFault = 0;
-  end           
 
   // unswizzle useful PTE bits
   assign {PTE_D, PTE_A} = PTEAccessBits[7:6];

pipelined/src/mmu/vm64check.sv

@@ -35,12 +35,16 @@ module vm64check (
   output logic                    UpperBitsUnequalPageFault
 );
 
-  logic                           eq_63_47, eq_46_38;
+  if (`XLEN == 64) begin
-
     assign SV39Mode = (SATP_MODE == `SV39);
 
     // page fault if upper bits aren't all the same
+    logic                           eq_63_47, eq_46_38;
     assign eq_46_38 = &(VAdr[46:38]) | ~|(VAdr[46:38]);
     assign eq_63_47 = &(VAdr[63:47]) | ~|(VAdr[63:47]); 
     assign UpperBitsUnequalPageFault = SV39Mode ? ~(eq_63_47 & eq_46_38) : ~eq_63_47;
+  end else begin
+    assign SV39Mode = 0;
+    assign UpperBitsUnequalPageFault = 0;
+  end
 endmodule

pipelined/testbench/testbench-linux.sv

@@ -155,7 +155,7 @@ module testbench;
   `define MCOUNTEREN  `CSR_BASE.csrm.mcounteren.MCOUNTERENreg.q
   `define SCOUNTEREN  `CSR_BASE.csrs.csrs.SCOUNTERENreg.q
   `define MSCRATCH    `CSR_BASE.csrm.MSCRATCHreg.q
-  `define SSCRATCH    `CSR_BASE.csrs.csrs.csrs.SSCRATCHreg.q
+  `define SSCRATCH    `CSR_BASE.csrs.csrs.SSCRATCHreg.q
   `define MTVEC       `CSR_BASE.csrm.MTVECreg.q
   `define STVEC       `CSR_BASE.csrs.csrs.STVECreg.q
   `define SATP        `CSR_BASE.csrs.csrs.genblk1.SATPreg.q