Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

benchmarks/coremark/Makefile

@@ -23,6 +23,8 @@ all: $(work_dir)/coremark.bare.riscv.elf.memfile
 run:
 	(cd ../../pipelined/regression && (time vsim -c -do "do wally-pipelined-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log))
 	cd ../../benchmarks/coremark/
+#	KMG: added post processing script to give out branch miss proportion along with other stats to the coremark test
+	python3 coremark-postprocess.py
 
 $(work_dir)/coremark.bare.riscv.elf.memfile: $(work_dir)/coremark.bare.riscv
 	riscv64-unknown-elf-objdump -D $< > $<.elf.objdump

benchmarks/coremark/coremark-postprocess.py

@@ -0,0 +1,46 @@
+#!/usr/bin/env python
+#########################################################
+#
+# coremark postprocessing script
+#
+# Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
+#
+# Created 2022-09-25
+#
+# Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+# files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
+# modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
+# is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+# OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+# OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+##################################################
+
+logFile = "../../benchmarks/coremark/work/coremark.sim.log"
+
+with open(logFile, "r") as logRead:
+    logLines = logRead.readlines()
+
+for lineNum in range(len(logLines)):
+    contents = logLines[lineNum].lower().split()
+    if "branches" in contents and "miss" in contents:
+        branchMisses = int(contents[-1])
+    elif "branches" in contents:
+        branchesTot = int(contents[-1])
+        branchLineNum = lineNum + 2
+
+logLines.insert(branchLineNum, "# Branches Miss/Total ratio " + str(branchMisses / branchesTot) + "\n")
+
+with open(logFile, "w") as logWrite:
+    logWrite.writelines(logLines)
+
+
+
+
+

pipelined/src/generic/mem/sram1p1rw.sv

@@ -66,22 +66,22 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) (
   // READ first SRAM model
   // ***************************************************************************
   end else begin
-    integer index2;
+    integer i;
     if (WIDTH%8 != 0) // handle msbs if not a multiple of 8
-      always_ff @(posedge clk) 
+      always @(posedge clk) 
         if (ce & we & bwe[WIDTH/8])
           RAM[addr][WIDTH-1:WIDTH-WIDTH%8] <= #1 din[WIDTH-1:WIDTH-WIDTH%8];
-    
+  
-    always_ff @(posedge clk) begin
+    always @(posedge clk) begin
       if(ce) begin
-        if(we) begin
-          for(index2 = 0; index2 < WIDTH/8; index2++) 
-            if(ce & we & bwe[index2])
-		      RAM[addr][index2*8 +: 8] <= #1 din[index2*8 +: 8];
-        end
         dout <= #1 RAM[addr];
+        if(we) begin
+          for(i = 0; i < WIDTH/8; i++) 
+            if(bwe[i])
+		          RAM[addr][i*8 +: 8] <= #1 din[i*8 +: 8];
+        end
       end
     end
-  end    
+  end 
 
 endmodule

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-endianness-01.reference_output

@@ -1,5 +1,5 @@
-aabbccdd # Test 5.3.2.4: M mode little endian load/store word of 0xAABBCCDD # NOTE: the memory was already filled with's so subword overwrite some, but not all of them. this is why the values are filled with deadbeefs, rather than 00's or ff's
+aabbccdd # Test 5.3.2.4: M mode little endian load/store word of 0xAABBCCDD NOTE: the memory was already filled with's so subword overwrite some, but not all of them. this is why the values are filled with deadbeefs, rather than 00's or ff's
-deadccdd # M mode little endian load/store halfword of 0xAABBCCDD # NOTE: since we're doing a store that matches the width of the load, we cut out all the sign extension
+deadccdd # M mode little endian load/store halfword of 0xAABBCCDD NOTE: since we're doing a store that matches the width of the load, we cut out all the sign extension
 deadbedd # M mode little endian load/store byte of 0xAABBCCDD
 ddccbbaa # M mode big endian load/store word of 0xDDCCBBAA
 deadbbaa # M mode big endian load/store halfword of 0xDDCCBBAA

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-endianness-01.S

@@ -24,7 +24,7 @@
 #include "WALLY-TEST-LIB-32.h" 
 
 RVTEST_ISA("RV32I")
-RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True; def NO_SAIL=True;",endianness)
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",endianness)
 
 INIT_TESTS
 
@@ -36,7 +36,7 @@ TRAP_HANDLER m
 
 // *** It appears Sail has the MBE, SBE, and UBE bits of mstatus hardwired to zero
 
-// M Mode little Endianness tests:
+// M Mode little endianness tests:
 
 li x28, 0xAABBCCDD
 li x29, 0x8000F000
@@ -57,10 +57,10 @@ sb x30, 0(t1) // test store byte, should save 0xDD
 addi t1, t1, 4
 addi a6, a6, 4
 
-li x28, 0x2000000000
+li x28, 0x20
-csrs mstatus, x28 // turn on big endianness for M mode
+csrs mstatush, x28 // turn on big endianness for M mode
 
-// M mode Big Endianness tests
+// M mode Big endianness tests
 // In big endian modes, all values are sign extended to the right, rather than left
 
 li x28, 0xAABBCCDD
@@ -82,8 +82,8 @@ sb x30, 0(t1) // test store byte, should save 0xAA
 addi t1, t1, 4
 addi a6, a6, 4
 
-li x28, 0x2000000000
+li x28, 0x20
-csrc mstatus, x28 // Turn off big endianness for M mode before going into the trap handler
+csrc mstatush, x28 // Turn off big endianness for M mode before going into the trap handler
 
 GOTO_S_MODE
 
@@ -110,8 +110,8 @@ addi a6, a6, 4
 
 GOTO_M_MODE // Go back to M mode to be able to toggle SBE bit of mstatus
 
-li x28, 0x1000000000
+li x28, 0x10
-csrs mstatus, x28 // turn on big endianness for S mode
+csrs mstatush, x28 // turn on big endianness for S mode
 
 GOTO_S_MODE 
 

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-xlen-01.reference_output

@@ -1,4 +1,4 @@
 00000000 # Test *** Number : Read out SXL, UXL of mstatus as 2 and 2 for 64 bit systems
 0000000a
-00000000 # read of read-only uxl, sxl bits after attmepted write
+0000000b # ecall from ending tests in M mode
-0000000a
+00000000

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-xlen-01.S

@@ -24,7 +24,7 @@
 #include "WALLY-TEST-LIB-64.h" 
 
 RVTEST_ISA("RV64I")
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",endianness)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",xlen)
 
 INIT_TESTS
 
@@ -39,13 +39,6 @@ sd x28, 0(t1) // should store 0xA00000000 to memory
 addi t1, t1, 8
 addi a6, a6, 8
 
-csrs mstatus, x29 // attempt to write to uxl and sxl, should not work
-csrr x28, mstatus
-and x28, x28, x29
-sd x28, 0(t1) // should store 0xA00000000 to memory
-addi t1, t1, 8
-addi a6, a6, 8
-
 END_TESTS
 
 TEST_STACK_AND_DATA