diff --git a/src/fpu/fclassify.sv b/src/fpu/fclassify.sv index 1a8f0fc19..bfc7a53dd 100644 --- a/src/fpu/fclassify.sv +++ b/src/fpu/fclassify.sv @@ -37,7 +37,7 @@ module fclassify import cvw::*; #(parameter cvw_t P) ( ); logic PInf, PZero, PNorm, PSubnorm; // is the input a positive infinity/zero/normal/subnormal - logic NInf, NZero, NNorm, NSubnorm; // is the input a negitive infinity/zero/normal/subnormal + logic NInf, NZero, NNorm, NSubnorm; // is the input a negative infinity/zero/normal/subnormal logic XNorm; // is the input normal // determine the sub categories diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index a9e187205..3d1a7bedd 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -215,7 +215,7 @@ module fctrl import cvw::*; #(parameter cvw_t P) ( // rounding modes: // 000 - round to nearest, ties to even // 001 - round twords 0 - round to min magnitude - // 010 - round down - round twords negitive infinity + // 010 - round down - round twords negative infinity // 011 - round up - round twords positive infinity // 100 - round to nearest, ties to max magnitude - round to nearest, ties away from zero // 111 - dynamic - choose FRM_REGW as rounding mode diff --git a/src/fpu/fcvt.sv b/src/fpu/fcvt.sv index 86321ae2f..d396fee95 100644 --- a/src/fpu/fcvt.sv +++ b/src/fpu/fcvt.sv @@ -80,7 +80,7 @@ module fcvt import cvw::*; #(parameter cvw_t P) ( /////////////////////////////////////////////////////////////////////////// // negation /////////////////////////////////////////////////////////////////////////// - // 1) negate the input if the input is a negitive singed integer + // 1) negate the input if the input is a negative singed integer // 2) trim the input to the proper size (kill the 32 most significant zeroes if needed) assign PosInt = Cs ? -Int : Int; @@ -182,7 +182,7 @@ module fcvt import cvw::*; #(parameter cvw_t P) ( assign Ce = {1'b0, OldExp} - (P.NE+1)'(P.BIAS) - {{P.NE-P.LOGCVTLEN+1{1'b0}}, (LeadingZeros)} + {2'b0, NewBias}; // find if the result is dnormal or underflows - // - if Calculated expoenent is 0 or negitive (and the input/result is not exactaly 0) + // - if Calculated expoenent is 0 or negative (and the input/result is not exactaly 0) // - can't underflow an integer to Fp conversion assign ResSubnormUf = (~|Ce | Ce[P.NE])&~XZero&~IntToFp; @@ -190,7 +190,7 @@ module fcvt import cvw::*; #(parameter cvw_t P) ( // shifter /////////////////////////////////////////////////////////////////////////// - // kill the shift if it's negitive + // kill the shift if it's negative // select the amount to shift by // fp -> int: // - shift left by CalcExp - essentially shifting until the unbiased exponent = 0 diff --git a/src/fpu/fma/fmaadd.sv b/src/fpu/fma/fmaadd.sv index 3d7dbbd81..98ff21491 100644 --- a/src/fpu/fma/fmaadd.sv +++ b/src/fpu/fma/fmaadd.sv @@ -42,8 +42,8 @@ module fmaadd import cvw::*; #(parameter cvw_t P) ( output logic [3*P.NF+3:0] Sm // the positive sum ); - logic [3*P.NF+3:0] PreSum, NegPreSum; // possibly negitive sum - logic NegSum; // was the sum negitive + logic [3*P.NF+3:0] PreSum, NegPreSum; // possibly negative sum + logic NegSum; // was the sum negative /////////////////////////////////////////////////////////////////////////////// // Addition @@ -54,8 +54,8 @@ module fmaadd import cvw::*; #(parameter cvw_t P) ( // Kill the product if the product is too small to effect the addition (determined in fma1.sv) assign PmKilled = {2*P.NF+2{~KillProd}}&Pm; // Do the addition - // - calculate a positive and negitive sum in parallel - // if there was a small negitive number killed in the alignment stage one needs to be subtracted from the sum + // - calculate a positive and negative sum in parallel + // if there was a small negative number killed in the alignment stage one needs to be subtracted from the sum // prod - addend where some of the addend is put into the sticky bit then don't add +1 from negation // ie ~(InvA&ASticky&~KillProd)&InvA = (~ASticky|KillProd)&InvA // addend - prod where product is killed (and not exactly zero) then don't add +1 from negation @@ -66,10 +66,10 @@ module fmaadd import cvw::*; #(parameter cvw_t P) ( // Choose the positive sum and accompanying LZA result. assign Sm = NegSum ? NegPreSum : PreSum; - // is the result negitive - // if p - z is the Sum negitive + // is the result negative + // if p - z is the Sum negative // if -p + z is the Sum positive - // if -p - z then the Sum is negitive + // if -p - z then the Sum is negative assign Ss = NegSum^Ps; assign Se = KillProd ? {2'b0, Ze} : Pe; endmodule diff --git a/src/fpu/fma/fmaalign.sv b/src/fpu/fma/fmaalign.sv index f9bddb9e3..efc4a4c5f 100644 --- a/src/fpu/fma/fmaalign.sv +++ b/src/fpu/fma/fmaalign.sv @@ -45,7 +45,7 @@ module fmaalign import cvw::*; #(parameter cvw_t P) ( /////////////////////////////////////////////////////////////////////////////// // determine the shift count for alignment - // - negitive means Z is larger, so shift Z left + // - negative means Z is larger, so shift Z left // - positive means the product is larger, so shift Z right // This could have been done using Pe, but ACnt is on the critical path so we replicate logic for speed assign ACnt = {2'b0, Xe} + {2'b0, Ye} - {2'b0, (P.NE)'(P.BIAS)} + (P.NE+2)'(P.NF+2) - {2'b0, Ze}; diff --git a/src/fpu/postproc/divshiftcalc.sv b/src/fpu/postproc/divshiftcalc.sv index 380f8f5e6..9e5de7173 100644 --- a/src/fpu/postproc/divshiftcalc.sv +++ b/src/fpu/postproc/divshiftcalc.sv @@ -36,7 +36,7 @@ module divshiftcalc import cvw::*; #(parameter cvw_t P) ( ); logic [P.LOGNORMSHIFTSZ-1:0] NormShift; // normalized result shift amount - logic [P.LOGNORMSHIFTSZ-1:0] DivSubnormShiftAmt; // subnormal result shift amount (killed if negitive) + logic [P.LOGNORMSHIFTSZ-1:0] DivSubnormShiftAmt; // subnormal result shift amount (killed if negative) logic [P.NE+1:0] DivSubnormShift; // subnormal result shift amount // is the result subnormal @@ -62,7 +62,7 @@ module divshiftcalc import cvw::*; #(parameter cvw_t P) ( // shift one more if the it's a minimally redundent radix 4 - one entire cycle needed for integer bit assign NormShift = (P.LOGNORMSHIFTSZ)'(P.NF); - // if the shift amount is negitive then don't shift (keep sticky bit) + // if the shift amount is negative then don't shift (keep sticky bit) // need to multiply the early termination shift by LOGR*DIVCOPIES = left shift of log2(LOGR*DIVCOPIES) assign DivSubnormShiftAmt = DivSubnormShiftPos ? DivSubnormShift[P.LOGNORMSHIFTSZ-1:0] : '0; assign DivShiftAmt = DivResSubnorm ? DivSubnormShiftAmt : NormShift; diff --git a/src/fpu/postproc/flags.sv b/src/fpu/postproc/flags.sv index 4a525bb0d..98ed0a34d 100644 --- a/src/fpu/postproc/flags.sv +++ b/src/fpu/postproc/flags.sv @@ -47,7 +47,7 @@ module flags import cvw::*; #(parameter cvw_t P) ( input logic Int64, // convert to 64 bit integer input logic Signed, // convert to a signed integer input logic [P.NE:0] CvtCe, // the calculated expoent - Cvt - input logic [1:0] CvtNegResMsbs, // the negitive integer result's most significant bits + input logic [1:0] CvtNegResMsbs, // the negative integer result's most significant bits // divsqrt input logic DivOp, // conversion opperation? input logic Sqrt, // Sqrt? @@ -122,7 +122,7 @@ module flags import cvw::*; #(parameter cvw_t P) ( // calulate overflow flag: // if the result is greater than or equal to the max exponent(not taking into account sign) - // | and the exponent isn't negitive + // | and the exponent isn't negative // | | if the input isnt infinity or NaN // | | | assign Overflow = ResExpGteMax & ~FullRe[P.NE+1]&~(InfIn|NaNIn|DivByZero); @@ -132,7 +132,7 @@ module flags import cvw::*; #(parameter cvw_t P) ( /////////////////////////////////////////////////////////////////////////////// // calculate underflow flag: detecting tininess after rounding - // the exponent is negitive + // the exponent is negative // | the result is subnormal // | | the result is normal and rounded from a Subnorm // | | | and if given an unbounded exponent the result does not round @@ -170,7 +170,7 @@ module flags import cvw::*; #(parameter cvw_t P) ( // invalid flag for integer result // if the input is NaN or infinity // | if the integer res overflows (out of range) - // | | if the input was negitive but ouputing to a unsigned number + // | | if the input was negative but ouputing to a unsigned number // | | | the res doesn't round to zero // | | | | or the res rounds up out of bounds // | | | | and the res didn't underflow diff --git a/src/fpu/postproc/resultsign.sv b/src/fpu/postproc/resultsign.sv index 9701cb7a6..0dd22c1f4 100644 --- a/src/fpu/postproc/resultsign.sv +++ b/src/fpu/postproc/resultsign.sv @@ -47,7 +47,7 @@ module resultsign( // determine the sign for a result of 0 // The IEEE754-2019 standard specifies: - // - the sign of an exact zero sum (with operands of diffrent signs) should be positive unless rounding toward negitive infinity + // - the sign of an exact zero sum (with operands of diffrent signs) should be positive unless rounding toward negative infinity // - when the exact result of an FMA opperation is non-zero, but is zero due to rounding, use the sign of the exact result // - if x = +0 or -0 then x+x=x and x-(-x)=x // - the sign of a product is the exclisive or or the opperand's signs @@ -63,10 +63,10 @@ module resultsign( assign Zeros = (FmaPs^FmaAs)&~(Round|Guard|Sticky)&~Mult ? Frm[1:0] == 2'b10 : FmaPs; // determine the sign of an infinity result - // is the result negitive - // if p - z is the Sum negitive + // is the result negative + // if p - z is the Sum negative // if -p + z is the Sum positive - // if -p - z then the Sum is negitive + // if -p - z then the Sum is negative assign Infs = ZInf ? FmaAs : FmaPs; // select the result sign diff --git a/src/fpu/postproc/specialcase.sv b/src/fpu/postproc/specialcase.sv index 5161bc645..5c7c59827 100644 --- a/src/fpu/postproc/specialcase.sv +++ b/src/fpu/postproc/specialcase.sv @@ -277,7 +277,7 @@ module specialcase import cvw::*; #(parameter cvw_t P) ( // IEEE 754 // select the overflow integer res - // - negitive infinity and out of range negitive input + // - negative infinity and out of range negative input // | int | long | // signed | -2^31 | -2^63 | // unsigned | 2^32-1 | 2^64-1 | @@ -291,7 +291,7 @@ module specialcase import cvw::*; #(parameter cvw_t P) ( // RISC-V // select the overflow integer res - // - negitive infinity and out of range negitive input + // - negative infinity and out of range negative input // | int | long | // signed | -2^31 | -2^63 | // unsigned | 0 | 0 | @@ -306,27 +306,27 @@ module specialcase import cvw::*; #(parameter cvw_t P) ( if(P.IEEE754) begin always_comb if(Signed) - if(Xs&~NaNIn) // signed negitive + if(Xs&~NaNIn) // signed negative if(Int64) OfIntRes = {1'b1, {P.XLEN-1{1'b0}}}; else OfIntRes = {{P.XLEN-32{1'b1}}, 1'b1, {31{1'b0}}}; else // signed positive if(Int64) OfIntRes = {1'b1, {P.XLEN-1{1'b0}}}; else OfIntRes = {{P.XLEN-32{1'b1}}, 1'b1, {31{1'b0}}}; else - if(Xs&~NaNIn) OfIntRes = {P.XLEN{1'b1}}; // unsigned negitive + if(Xs&~NaNIn) OfIntRes = {P.XLEN{1'b1}}; // unsigned negative else OfIntRes = {P.XLEN{1'b1}}; // unsigned positive end // if (P.IEEE754) else begin always_comb if(Signed) - if(Xs&~NaNIn) // signed negitive + if(Xs&~NaNIn) // signed negative if(Int64) OfIntRes = {1'b1, {P.XLEN-1{1'b0}}}; else OfIntRes = {{P.XLEN-32{1'b1}}, 1'b1, {31{1'b0}}}; else // signed positive if(Int64) OfIntRes = {1'b0, {P.XLEN-1{1'b1}}}; else OfIntRes = {{P.XLEN-32{1'b0}}, 1'b0, {31{1'b1}}}; else - if(Xs&~NaNIn) OfIntRes = {P.XLEN{1'b0}}; // unsigned negitive + if(Xs&~NaNIn) OfIntRes = {P.XLEN{1'b0}}; // unsigned negative else OfIntRes = {P.XLEN{1'b1}}; // unsigned positive end // else: !if(P.IEEE754) @@ -334,7 +334,7 @@ module specialcase import cvw::*; #(parameter cvw_t P) ( // select the integer output // - if the input is invalid (out of bounds NaN or Inf) then output overflow res // - if the input underflows - // - if rounding and signed opperation and negitive input, output -1 + // - if rounding and signed opperation and negative input, output -1 // - otherwise output a rounded 0 // - otherwise output the normal res (trmined and sign extended if nessisary) always_comb