From 8c67a76912203a60fcd8aa615f1d360608077c9f Mon Sep 17 00:00:00 2001 From: Kunlin Han Date: Fri, 8 Mar 2024 11:22:04 -0800 Subject: [PATCH 01/12] Remove all #delay from non-testbench. --- src/cache/cachefsm.sv | 4 +- src/cache/cacheway.sv | 16 +-- src/ebu/buscachefsm.sv | 4 +- src/ebu/busfsm.sv | 4 +- src/fpu/fctrl.sv | 2 +- src/fpu/fdivsqrt/fdivsqrtfsm.sv | 12 +- src/fpu/fregfile.sv | 6 +- src/generic/flop/flop.sv | 2 +- src/generic/flop/flopen.sv | 2 +- src/generic/flop/flopenl.sv | 4 +- src/generic/flop/flopenr.sv | 4 +- src/generic/flop/flopenrc.sv | 6 +- src/generic/flop/flopens.sv | 4 +- src/generic/flop/flopr.sv | 4 +- src/generic/flop/synchronizer.sv | 4 +- src/generic/mem/ram1p1rwbe.sv | 6 +- src/generic/mem/ram1p1rwe.sv | 4 +- src/generic/mem/ram2p1r1wbe.sv | 4 +- src/hazard/hazard.sv | 18 +-- src/ieu/regfile.sv | 4 +- src/ifu/bpred/RASPredictor.sv | 2 +- src/ifu/bpred/localrepairbp.sv | 6 +- src/ifu/spill.sv | 4 +- src/lsu/align.sv | 4 +- src/privileged/csrc.sv | 8 +- src/privileged/csrsr.sv | 112 ++++++++--------- src/uncore/clint_apb.sv | 4 +- src/uncore/gpio_apb.sv | 76 ++++++------ src/uncore/plic_apb.sv | 58 ++++----- src/uncore/ram_ahb.sv | 4 +- src/uncore/spi_apb.sv | 58 ++++----- src/uncore/uartPC16550D.sv | 198 +++++++++++++++---------------- testbench/common/wallyTracer.sv | 82 ++++++------- testbench/sdc/sdModel.sv | 2 +- 34 files changed, 366 insertions(+), 366 deletions(-) diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index 4af89b08e..3ad8edbc2 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -110,8 +110,8 @@ module cachefsm import cvw::*; #(parameter cvw_t P, flop #(1) resetDelayReg(.clk, .d(reset), .q(resetDelay)); always_ff @(posedge clk) - if (reset | FlushStage) CurrState <= #1 STATE_READY; - else CurrState <= #1 NextState; + if (reset | FlushStage) CurrState <= STATE_READY; + else CurrState <= NextState; always_comb begin NextState = STATE_READY; diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index 678f7acac..dbabb296e 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -159,12 +159,12 @@ module cacheway import cvw::*; #(parameter cvw_t P, ///////////////////////////////////////////////////////////////////////////////////////////// always_ff @(posedge clk) begin // Valid bit array, - if (reset) ValidBits <= #1 '0; + if (reset) ValidBits <= '0; if(CacheEn) begin - ValidWay <= #1 ValidBits[CacheSetTag]; - if(InvalidateCache) ValidBits <= #1 '0; // exclusion-tag: dcache invalidateway - else if (SetValidEN) ValidBits[CacheSetData] <= #1 SetValidWay; - else if (ClearValidEN) ValidBits[CacheSetData] <= #1 '0; // exclusion-tag: icache ClearValidBits + ValidWay <= ValidBits[CacheSetTag]; + if(InvalidateCache) ValidBits <= '0; // exclusion-tag: dcache invalidateway + else if (SetValidEN) ValidBits[CacheSetData] <= SetValidWay; + else if (ClearValidEN) ValidBits[CacheSetData] <= '0; // exclusion-tag: icache ClearValidBits end end @@ -176,10 +176,10 @@ module cacheway import cvw::*; #(parameter cvw_t P, if (!READ_ONLY_CACHE) begin:dirty always_ff @(posedge clk) begin // reset is optional. Consider merging with TAG array in the future. - //if (reset) DirtyBits <= #1 {NUMLINES{1'b0}}; + //if (reset) DirtyBits <= {NUMLINES{1'b0}}; if(CacheEn) begin - Dirty <= #1 DirtyBits[CacheSetTag]; - if((SetDirtyWay | ClearDirtyWay) & ~FlushStage) DirtyBits[CacheSetData] <= #1 SetDirtyWay; // exclusion-tag: cache UpdateDirty + Dirty <= DirtyBits[CacheSetTag]; + if((SetDirtyWay | ClearDirtyWay) & ~FlushStage) DirtyBits[CacheSetData] <= SetDirtyWay; // exclusion-tag: cache UpdateDirty end end end else assign Dirty = 1'b0; diff --git a/src/ebu/buscachefsm.sv b/src/ebu/buscachefsm.sv index e1fded607..b0f28966e 100644 --- a/src/ebu/buscachefsm.sv +++ b/src/ebu/buscachefsm.sv @@ -82,8 +82,8 @@ module buscachefsm #( assign BusWrite = (CacheBusRW[0] | BusCMOZero) & ~READ_ONLY_CACHE; always_ff @(posedge HCLK) - if (~HRESETn | Flush) CurrState <= #1 ADR_PHASE; - else CurrState <= #1 NextState; + if (~HRESETn | Flush) CurrState <= ADR_PHASE; + else CurrState <= NextState; always_comb begin case(CurrState) diff --git a/src/ebu/busfsm.sv b/src/ebu/busfsm.sv index e49a6313a..11ba896e4 100644 --- a/src/ebu/busfsm.sv +++ b/src/ebu/busfsm.sv @@ -55,8 +55,8 @@ module busfsm #( busstatetype CurrState, NextState; always_ff @(posedge HCLK) - if (~HRESETn | Flush) CurrState <= #1 ADR_PHASE; - else CurrState <= #1 NextState; + if (~HRESETn | Flush) CurrState <= ADR_PHASE; + else CurrState <= NextState; always_comb begin case(CurrState) diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index c61629c13..d4d43428b 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -250,7 +250,7 @@ module fctrl import cvw::*; #(parameter cvw_t P) ( /* verilator lint_on CASEINCOMPLETE */ // unswizzle control bits - assign #1 {FRegWriteD, FWriteIntD, FResSelD, PostProcSelD, OpCtrlD, FDivStartD, IllegalFPUInstrD, FCvtIntD, ZfaD} = ControlsD; + assign {FRegWriteD, FWriteIntD, FResSelD, PostProcSelD, OpCtrlD, FDivStartD, IllegalFPUInstrD, FCvtIntD, ZfaD} = ControlsD; // rounding modes: // 000 - round to nearest, ties to even diff --git a/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/src/fpu/fdivsqrt/fdivsqrtfsm.sv index f7d21e5d8..8975edeb6 100644 --- a/src/fpu/fdivsqrt/fdivsqrtfsm.sv +++ b/src/fpu/fdivsqrt/fdivsqrtfsm.sv @@ -63,17 +63,17 @@ module fdivsqrtfsm import cvw::*; #(parameter cvw_t P) ( always_ff @(posedge clk) begin if (reset | FlushE) begin - state <= #1 IDLE; + state <= IDLE; end else if (IFDivStartE) begin // IFDivStartE implies stat is IDLE step <= CyclesE; - if (SpecialCaseE) state <= #1 DONE; - else state <= #1 BUSY; + if (SpecialCaseE) state <= DONE; + else state <= BUSY; end else if (state == BUSY) begin - if (step == 1 | WZeroE) state <= #1 DONE; // finished steps or terminate early on zero residual + if (step == 1 | WZeroE) state <= DONE; // finished steps or terminate early on zero residual step <= step - 1; end else if (state == DONE) begin // Can't still be stalled in configs tested, but keep this check for paranoia - if (StallM) state <= #1 DONE; // exclusion-tag: fdivsqrtfsm stallm - else state <= #1 IDLE; + if (StallM) state <= DONE; // exclusion-tag: fdivsqrtfsm stallm + else state <= IDLE; end end diff --git a/src/fpu/fregfile.sv b/src/fpu/fregfile.sv index 2de41088b..b78c1f430 100644 --- a/src/fpu/fregfile.sv +++ b/src/fpu/fregfile.sv @@ -47,8 +47,8 @@ module fregfile #(parameter FLEN) ( if (reset) for(i=0; i<32; i++) rf[i] <= 0; else if (we4) rf[a4] <= wd4; - assign #2 rd1 = rf[a1]; - assign #2 rd2 = rf[a2]; - assign #2 rd3 = rf[a3]; + assign rd1 = rf[a1]; + assign rd2 = rf[a2]; + assign rd3 = rf[a3]; endmodule // regfile diff --git a/src/generic/flop/flop.sv b/src/generic/flop/flop.sv index b7e7a82ee..662b9865e 100644 --- a/src/generic/flop/flop.sv +++ b/src/generic/flop/flop.sv @@ -31,6 +31,6 @@ module flop #(parameter WIDTH = 8) ( output logic [WIDTH-1:0] q); always_ff @(posedge clk) - q <= #1 d; + q <= d; endmodule diff --git a/src/generic/flop/flopen.sv b/src/generic/flop/flopen.sv index f1db84776..e56488a90 100644 --- a/src/generic/flop/flopen.sv +++ b/src/generic/flop/flopen.sv @@ -31,6 +31,6 @@ module flopen #(parameter WIDTH = 8) ( output logic [WIDTH-1:0] q); always_ff @(posedge clk) - if (en) q <= #1 d; + if (en) q <= d; endmodule diff --git a/src/generic/flop/flopenl.sv b/src/generic/flop/flopenl.sv index 08b6590a8..310be2426 100644 --- a/src/generic/flop/flopenl.sv +++ b/src/generic/flop/flopenl.sv @@ -32,7 +32,7 @@ module flopenl #(parameter WIDTH = 8, parameter type TYPE=logic [WIDTH-1:0]) ( output TYPE q); always_ff @(posedge clk) - if (load) q <= #1 val; - else if (en) q <= #1 d; + if (load) q <= val; + else if (en) q <= d; endmodule diff --git a/src/generic/flop/flopenr.sv b/src/generic/flop/flopenr.sv index 565fbfa7a..1973b444b 100644 --- a/src/generic/flop/flopenr.sv +++ b/src/generic/flop/flopenr.sv @@ -31,7 +31,7 @@ module flopenr #(parameter WIDTH = 8) ( output logic [WIDTH-1:0] q); always_ff @(posedge clk) - if (reset) q <= #1 0; - else if (en) q <= #1 d; + if (reset) q <= 0; + else if (en) q <= d; endmodule diff --git a/src/generic/flop/flopenrc.sv b/src/generic/flop/flopenrc.sv index 983fae5f2..64d5761a6 100644 --- a/src/generic/flop/flopenrc.sv +++ b/src/generic/flop/flopenrc.sv @@ -31,9 +31,9 @@ module flopenrc #(parameter WIDTH = 8) ( output logic [WIDTH-1:0] q); always_ff @(posedge clk) - if (reset) q <= #1 0; + if (reset) q <= 0; else if (en) - if (clear) q <= #1 0; - else q <= #1 d; + if (clear) q <= 0; + else q <= d; endmodule diff --git a/src/generic/flop/flopens.sv b/src/generic/flop/flopens.sv index 11c128393..d5969128c 100644 --- a/src/generic/flop/flopens.sv +++ b/src/generic/flop/flopens.sv @@ -31,8 +31,8 @@ module flopens #(parameter WIDTH = 8) ( output logic [WIDTH-1:0] q); always_ff @(posedge clk) - if (set) q <= #1 1; - else if (en) q <= #1 d; + if (set) q <= 1; + else if (en) q <= d; endmodule diff --git a/src/generic/flop/flopr.sv b/src/generic/flop/flopr.sv index b3edcbdf9..538d29f3c 100644 --- a/src/generic/flop/flopr.sv +++ b/src/generic/flop/flopr.sv @@ -31,7 +31,7 @@ module flopr #(parameter WIDTH = 8) ( output logic [WIDTH-1:0] q); always_ff @(posedge clk) - if (reset) q <= #1 0; - else q <= #1 d; + if (reset) q <= 0; + else q <= d; endmodule diff --git a/src/generic/flop/synchronizer.sv b/src/generic/flop/synchronizer.sv index d4a63cd53..35df909b7 100644 --- a/src/generic/flop/synchronizer.sv +++ b/src/generic/flop/synchronizer.sv @@ -33,8 +33,8 @@ module synchronizer ( logic mid; always_ff @(posedge clk) begin - mid <= #1 d; - q <= #1 mid; + mid <= d; + q <= mid; end endmodule diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv index ccfce5da2..e833ddfd1 100644 --- a/src/generic/mem/ram1p1rwbe.sv +++ b/src/generic/mem/ram1p1rwbe.sv @@ -97,7 +97,7 @@ module ram1p1rwbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44, PRE /* // Alternate read logic reads the old contents of mem[addr]. Increases setup time and adds dout reg, but reduces clk to q always_ff @(posedge clk) - if(ce) dout <= #1 mem[addr]; */ + if(ce) dout <= mem[addr]; */ // Write divided into part for bytes and part for extra msbs // Questa sim version 2022.3_2 does not allow multiple drivers for RAM when using always_ff. @@ -106,12 +106,12 @@ module ram1p1rwbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44, PRE always @(posedge clk) if (ce & we) for(i = 0; i < WIDTH/8; i++) - if(bwe[i]) RAM[addr][i*8 +: 8] <= #1 din[i*8 +: 8]; + if(bwe[i]) RAM[addr][i*8 +: 8] <= din[i*8 +: 8]; if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8 always @(posedge clk) if (ce & we & bwe[WIDTH/8]) - RAM[addr][WIDTH-1:WIDTH-WIDTH%8] <= #1 din[WIDTH-1:WIDTH-WIDTH%8]; + RAM[addr][WIDTH-1:WIDTH-WIDTH%8] <= din[WIDTH-1:WIDTH-WIDTH%8]; end endmodule diff --git a/src/generic/mem/ram1p1rwe.sv b/src/generic/mem/ram1p1rwe.sv index ebe7e336b..660afdff2 100644 --- a/src/generic/mem/ram1p1rwe.sv +++ b/src/generic/mem/ram1p1rwe.sv @@ -78,7 +78,7 @@ module ram1p1rwe import cvw::* ; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44) ( /* // Alternate read logic reads the old contents of mem[addr]. Increases setup time and adds dout reg, but reduces clk to q always_ff @(posedge clk) - if(ce) dout <= #1 mem[addr]; */ + if(ce) dout <= mem[addr]; */ // Write divided into part for bytes and part for extra msbs // Questa sim version 2022.3_2 does not allow multiple drivers for RAM when using always_ff. @@ -90,6 +90,6 @@ module ram1p1rwe import cvw::* ; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44) ( // so we can never get we=1, ce=0 for I$. if (ce & we) // coverage on - RAM[addr] <= #1 din; + RAM[addr] <= din; end endmodule diff --git a/src/generic/mem/ram2p1r1wbe.sv b/src/generic/mem/ram2p1r1wbe.sv index 0945684d3..424999291 100644 --- a/src/generic/mem/ram2p1r1wbe.sv +++ b/src/generic/mem/ram2p1r1wbe.sv @@ -129,13 +129,13 @@ module ram2p1r1wbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=1024, WIDTH=68) always @(posedge clk) if (ce2 & we2) for(i = 0; i < WIDTH/8; i++) - if(bwe2[i]) mem[wa2][i*8 +: 8] <= #1 wd2[i*8 +: 8]; + if(bwe2[i]) mem[wa2][i*8 +: 8] <= wd2[i*8 +: 8]; // coverage on if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8 always @(posedge clk) if (ce2 & we2 & bwe2[WIDTH/8]) - mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= #1 wd2[WIDTH-1:WIDTH-WIDTH%8]; + mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= wd2[WIDTH-1:WIDTH-WIDTH%8]; end endmodule diff --git a/src/hazard/hazard.sv b/src/hazard/hazard.sv index 140c3e74e..9c7900cc4 100644 --- a/src/hazard/hazard.sv +++ b/src/hazard/hazard.sv @@ -93,12 +93,12 @@ module hazard import cvw::*; #(parameter cvw_t P) ( // Stall each stage for cause or if the next stage is stalled // coverage off: StallFCause is always 0 - assign #1 StallF = StallFCause | StallD; + assign StallF = StallFCause | StallD; // coverage on - assign #1 StallD = StallDCause | StallE; - assign #1 StallE = StallECause | StallM; - assign #1 StallM = StallMCause | StallW; - assign #1 StallW = StallWCause; + assign StallD = StallDCause | StallE; + assign StallE = StallECause | StallM; + assign StallM = StallMCause | StallW; + assign StallW = StallWCause; // detect the first stage that is not stalled assign LatestUnstalledD = ~StallD & StallF; @@ -107,8 +107,8 @@ module hazard import cvw::*; #(parameter cvw_t P) ( assign LatestUnstalledW = ~StallW & StallM; // Each stage flushes if the previous stage is the last one stalled (for cause) or the system has reason to flush - assign #1 FlushD = LatestUnstalledD | FlushDCause; - assign #1 FlushE = LatestUnstalledE | FlushECause; - assign #1 FlushM = LatestUnstalledM | FlushMCause; - assign #1 FlushW = LatestUnstalledW | FlushWCause; + assign FlushD = LatestUnstalledD | FlushDCause; + assign FlushE = LatestUnstalledE | FlushECause; + assign FlushM = LatestUnstalledM | FlushMCause; + assign FlushW = LatestUnstalledW | FlushWCause; endmodule diff --git a/src/ieu/regfile.sv b/src/ieu/regfile.sv index bf6990ea9..523964914 100644 --- a/src/ieu/regfile.sv +++ b/src/ieu/regfile.sv @@ -53,6 +53,6 @@ module regfile #(parameter XLEN, E_SUPPORTED) ( if (reset) for(i=1; i1 cycle to respond // word aligned reads - if (P.XLEN==64) assign #2 entry = {PADDR[15:3], 3'b000}; - else assign #2 entry = {PADDR[15:2], 2'b00}; + if (P.XLEN==64) assign entry = {PADDR[15:3], 3'b000}; + else assign entry = {PADDR[15:2], 2'b00}; // DH 2/20/21: Eventually allow MTIME to run off a separate clock // This will require synchronizing MTIME to the system clock diff --git a/src/uncore/gpio_apb.sv b/src/uncore/gpio_apb.sv index 3b4ae1cb0..430b44111 100644 --- a/src/uncore/gpio_apb.sv +++ b/src/uncore/gpio_apb.sv @@ -70,33 +70,33 @@ module gpio_apb import cvw::*; #(parameter cvw_t P) ( input_en <= 0; output_en <= 0; // *** synch reset not yet implemented [DH: can we delete this comment? Check if a sync reset is required] - output_val <= #1 0; - rise_ie <= #1 0; - rise_ip <= #1 0; - fall_ie <= #1 0; - fall_ip <= #1 0; - high_ie <= #1 0; - high_ip <= #1 0; - low_ie <= #1 0; - low_ip <= #1 0; - iof_en <= #1 0; - iof_sel <= #1 0; - out_xor <= #1 0; + output_val <= 0; + rise_ie <= 0; + rise_ip <= 0; + fall_ie <= 0; + fall_ip <= 0; + high_ie <= 0; + high_ip <= 0; + low_ie <= 0; + low_ip <= 0; + iof_en <= 0; + iof_sel <= 0; + out_xor <= 0; end else begin // writes // According to FE310 spec: Once the interrupt is pending, it will remain set until a 1 is written to the *_ip register at that bit. /* verilator lint_off CASEINCOMPLETE */ if (memwrite) case(entry) - 8'h04: input_en <= #1 Din; - 8'h08: output_en <= #1 Din; - 8'h0C: output_val <= #1 Din; - 8'h18: rise_ie <= #1 Din; - 8'h20: fall_ie <= #1 Din; - 8'h28: high_ie <= #1 Din; - 8'h30: low_ie <= #1 Din; - 8'h38: iof_en <= #1 Din; - 8'h3C: iof_sel <= #1 Din; - 8'h40: out_xor <= #1 Din; + 8'h04: input_en <= Din; + 8'h08: output_en <= Din; + 8'h0C: output_val <= Din; + 8'h18: rise_ie <= Din; + 8'h20: fall_ie <= Din; + 8'h28: high_ie <= Din; + 8'h30: low_ie <= Din; + 8'h38: iof_en <= Din; + 8'h3C: iof_sel <= Din; + 8'h40: out_xor <= Din; endcase /* verilator lint_on CASEINCOMPLETE */ @@ -111,22 +111,22 @@ module gpio_apb import cvw::*; #(parameter cvw_t P) ( else low_ip <= low_ip | ~input3d; case(entry) // flop to sample inputs - 8'h00: Dout <= #1 input_val; - 8'h04: Dout <= #1 input_en; - 8'h08: Dout <= #1 output_en; - 8'h0C: Dout <= #1 output_val; - 8'h18: Dout <= #1 rise_ie; - 8'h1C: Dout <= #1 rise_ip; - 8'h20: Dout <= #1 fall_ie; - 8'h24: Dout <= #1 fall_ip; - 8'h28: Dout <= #1 high_ie; - 8'h2C: Dout <= #1 high_ip; - 8'h30: Dout <= #1 low_ie; - 8'h34: Dout <= #1 low_ip; - 8'h38: Dout <= #1 iof_en; - 8'h3C: Dout <= #1 iof_sel; - 8'h40: Dout <= #1 out_xor; - default: Dout <= #1 0; + 8'h00: Dout <= input_val; + 8'h04: Dout <= input_en; + 8'h08: Dout <= output_en; + 8'h0C: Dout <= output_val; + 8'h18: Dout <= rise_ie; + 8'h1C: Dout <= rise_ip; + 8'h20: Dout <= fall_ie; + 8'h24: Dout <= fall_ip; + 8'h28: Dout <= high_ie; + 8'h2C: Dout <= high_ip; + 8'h30: Dout <= low_ie; + 8'h34: Dout <= low_ip; + 8'h38: Dout <= iof_en; + 8'h3C: Dout <= iof_sel; + 8'h40: Dout <= out_xor; + default: Dout <= 0; endcase end diff --git a/src/uncore/plic_apb.sv b/src/uncore/plic_apb.sv index 4c0602353..35b4f7e7b 100644 --- a/src/uncore/plic_apb.sv +++ b/src/uncore/plic_apb.sv @@ -107,48 +107,48 @@ module plic_apb import cvw::*; #(parameter cvw_t P) ( always @(posedge PCLK) begin // resetting if (~PRESETn) begin - intPriority <= #1 '0; - intEn <= #1 '0; - intThreshold <= #1 '0; - intInProgress <= #1 '0; + intPriority <= '0; + intEn <= '0; + intThreshold <= '0; + intInProgress <= '0; // writing end else begin if (memwrite) casez(entry) - 24'h0000??: intPriority[entry[7:2]] <= #1 Din[2:0]; - 24'h002000: intEn[0][PLIC_NUM_SRC_MIN_32:1] <= #1 Din[PLIC_NUM_SRC_MIN_32:1]; - 24'h002080: intEn[1][PLIC_NUM_SRC_MIN_32:1] <= #1 Din[PLIC_NUM_SRC_MIN_32:1]; - 24'h002004: if (P.PLIC_NUM_SRC >= 32) intEn[0][PLIC_SRC_TOP:PLIC_SRC_BOT] <= #1 Din[PLIC_SRC_DINTOP:0]; - 24'h002084: if (P.PLIC_NUM_SRC >= 32) intEn[1][PLIC_SRC_TOP:PLIC_SRC_BOT] <= #1 Din[PLIC_SRC_DINTOP:0]; - 24'h200000: intThreshold[0] <= #1 Din[2:0]; - 24'h200004: intInProgress <= #1 intInProgress & ~(One << (Din[5:0]-1)); // lower "InProgress" to signify completion - 24'h201000: intThreshold[1] <= #1 Din[2:0]; - 24'h201004: intInProgress <= #1 intInProgress & ~(One << (Din[5:0]-1)); // lower "InProgress" to signify completion + 24'h0000??: intPriority[entry[7:2]] <= Din[2:0]; + 24'h002000: intEn[0][PLIC_NUM_SRC_MIN_32:1] <= Din[PLIC_NUM_SRC_MIN_32:1]; + 24'h002080: intEn[1][PLIC_NUM_SRC_MIN_32:1] <= Din[PLIC_NUM_SRC_MIN_32:1]; + 24'h002004: if (P.PLIC_NUM_SRC >= 32) intEn[0][PLIC_SRC_TOP:PLIC_SRC_BOT] <= Din[PLIC_SRC_DINTOP:0]; + 24'h002084: if (P.PLIC_NUM_SRC >= 32) intEn[1][PLIC_SRC_TOP:PLIC_SRC_BOT] <= Din[PLIC_SRC_DINTOP:0]; + 24'h200000: intThreshold[0] <= Din[2:0]; + 24'h200004: intInProgress <= intInProgress & ~(One << (Din[5:0]-1)); // lower "InProgress" to signify completion + 24'h201000: intThreshold[1] <= Din[2:0]; + 24'h201004: intInProgress <= intInProgress & ~(One << (Din[5:0]-1)); // lower "InProgress" to signify completion endcase // Read synchronously because a read can have side effect of changing intInProgress if (memread) begin casez(entry) - 24'h000000: Dout <= #1 32'b0; // there is no intPriority[0] - 24'h0000??: Dout <= #1 {29'b0,intPriority[entry[7:2]]}; - 24'h001000: Dout <= #1 {{(31-PLIC_NUM_SRC_MIN_32){1'b0}},intPending[PLIC_NUM_SRC_MIN_32:1],1'b0}; - 24'h002000: Dout <= #1 {{(31-PLIC_NUM_SRC_MIN_32){1'b0}},intEn[0][PLIC_NUM_SRC_MIN_32:1],1'b0}; - 24'h001004: if (P.PLIC_NUM_SRC >= 32) Dout <= #1 {{(PLIC_SRC_EXT){1'b0}},intPending[PLIC_SRC_TOP:PLIC_SRC_BOT]}; - 24'h002004: if (P.PLIC_NUM_SRC >= 32) Dout <= #1 {{(PLIC_SRC_EXT){1'b0}},intEn[0][PLIC_SRC_TOP:PLIC_SRC_BOT]}; - 24'h002080: Dout <= #1 {{(31-PLIC_NUM_SRC_MIN_32){1'b0}},intEn[1][PLIC_NUM_SRC_MIN_32:1],1'b0}; - 24'h002084: if (P.PLIC_NUM_SRC >= 32) Dout <= #1 {{(PLIC_SRC_EXT){1'b0}},intEn[1][PLIC_SRC_TOP:PLIC_SRC_BOT]}; - 24'h200000: Dout <= #1 {29'b0,intThreshold[0]}; + 24'h000000: Dout <= 32'b0; // there is no intPriority[0] + 24'h0000??: Dout <= {29'b0,intPriority[entry[7:2]]}; + 24'h001000: Dout <= {{(31-PLIC_NUM_SRC_MIN_32){1'b0}},intPending[PLIC_NUM_SRC_MIN_32:1],1'b0}; + 24'h002000: Dout <= {{(31-PLIC_NUM_SRC_MIN_32){1'b0}},intEn[0][PLIC_NUM_SRC_MIN_32:1],1'b0}; + 24'h001004: if (P.PLIC_NUM_SRC >= 32) Dout <= {{(PLIC_SRC_EXT){1'b0}},intPending[PLIC_SRC_TOP:PLIC_SRC_BOT]}; + 24'h002004: if (P.PLIC_NUM_SRC >= 32) Dout <= {{(PLIC_SRC_EXT){1'b0}},intEn[0][PLIC_SRC_TOP:PLIC_SRC_BOT]}; + 24'h002080: Dout <= {{(31-PLIC_NUM_SRC_MIN_32){1'b0}},intEn[1][PLIC_NUM_SRC_MIN_32:1],1'b0}; + 24'h002084: if (P.PLIC_NUM_SRC >= 32) Dout <= {{(PLIC_SRC_EXT){1'b0}},intEn[1][PLIC_SRC_TOP:PLIC_SRC_BOT]}; + 24'h200000: Dout <= {29'b0,intThreshold[0]}; 24'h200004: begin - Dout <= #1 {26'b0,intClaim[0]}; - intInProgress <= #1 intInProgress | (One << (intClaim[0]-1)); // claimed requests are currently in progress of being serviced until they are completed + Dout <= {26'b0,intClaim[0]}; + intInProgress <= intInProgress | (One << (intClaim[0]-1)); // claimed requests are currently in progress of being serviced until they are completed end - 24'h201000: Dout <= #1 {29'b0,intThreshold[1]}; + 24'h201000: Dout <= {29'b0,intThreshold[1]}; 24'h201004: begin - Dout <= #1 {26'b0,intClaim[1]}; - intInProgress <= #1 intInProgress | (One << (intClaim[1]-1)); // claimed requests are currently in progress of being serviced until they are completed + Dout <= {26'b0,intClaim[1]}; + intInProgress <= intInProgress | (One << (intClaim[1]-1)); // claimed requests are currently in progress of being serviced until they are completed end - default: Dout <= #1 32'h0; // invalid access + default: Dout <= 32'h0; // invalid access endcase - end else Dout <= #1 32'h0; + end else Dout <= 32'h0; end end diff --git a/src/uncore/ram_ahb.sv b/src/uncore/ram_ahb.sv index 98bdfcb09..d26161f4f 100644 --- a/src/uncore/ram_ahb.sv +++ b/src/uncore/ram_ahb.sv @@ -86,8 +86,8 @@ module ram_ahb import cvw::*; #(parameter cvw_t P, statetype CurrState, NextState; always_ff @(posedge HCLK) - if (~HRESETn) CurrState <= #1 READY; - else CurrState <= #1 NextState; + if (~HRESETn) CurrState <= READY; + else CurrState <= NextState; always_comb begin case(CurrState) diff --git a/src/uncore/spi_apb.sv b/src/uncore/spi_apb.sv index 626487f91..3f34e938e 100644 --- a/src/uncore/spi_apb.sv +++ b/src/uncore/spi_apb.sv @@ -136,19 +136,19 @@ module spi_apb import cvw::*; #(parameter cvw_t P) ( // Register access always_ff@(posedge PCLK, negedge PRESETn) if (~PRESETn) begin - SckDiv <= #1 12'd3; - SckMode <= #1 2'b0; - ChipSelectID <= #1 2'b0; - ChipSelectDef <= #1 4'b1111; - ChipSelectMode <= #1 0; - Delay0 <= #1 {8'b1,8'b1}; - Delay1 <= #1 {8'b0,8'b1}; - Format <= #1 {5'b10000}; - TransmitData <= #1 9'b0; - TransmitWatermark <= #1 3'b0; - ReceiveWatermark <= #1 3'b0; - InterruptEnable <= #1 2'b0; - InterruptPending <= #1 2'b0; + SckDiv <= 12'd3; + SckMode <= 2'b0; + ChipSelectID <= 2'b0; + ChipSelectDef <= 4'b1111; + ChipSelectMode <= 0; + Delay0 <= {8'b1,8'b1}; + Delay1 <= {8'b0,8'b1}; + Format <= {5'b10000}; + TransmitData <= 9'b0; + TransmitWatermark <= 3'b0; + ReceiveWatermark <= 3'b0; + InterruptEnable <= 2'b0; + InterruptPending <= 2'b0; end else begin // writes @@ -176,21 +176,21 @@ module spi_apb import cvw::*; #(parameter cvw_t P) ( InterruptPending[1] <= RecieveWriteMark; case(Entry) // Flop to sample inputs - 8'h00: Dout <= #1 {20'b0, SckDiv}; - 8'h04: Dout <= #1 {30'b0, SckMode}; - 8'h10: Dout <= #1 {30'b0, ChipSelectID}; - 8'h14: Dout <= #1 {28'b0, ChipSelectDef}; - 8'h18: Dout <= #1 {30'b0, ChipSelectMode}; - 8'h28: Dout <= #1 {8'b0, Delay0[15:8], 8'b0, Delay0[7:0]}; - 8'h2C: Dout <= #1 {8'b0, Delay1[15:8], 8'b0, Delay1[7:0]}; - 8'h40: Dout <= #1 {12'b0, Format[4:1], 13'b0, Format[0], 2'b0}; - 8'h48: Dout <= #1 {23'b0, TransmitFIFOWriteFull, 8'b0}; - 8'h4C: Dout <= #1 {23'b0, ReceiveFIFOReadEmpty, ReceiveData[7:0]}; - 8'h50: Dout <= #1 {29'b0, TransmitWatermark}; - 8'h54: Dout <= #1 {29'b0, ReceiveWatermark}; - 8'h70: Dout <= #1 {30'b0, InterruptEnable}; - 8'h74: Dout <= #1 {30'b0, InterruptPending}; - default: Dout <= #1 32'b0; + 8'h00: Dout <= {20'b0, SckDiv}; + 8'h04: Dout <= {30'b0, SckMode}; + 8'h10: Dout <= {30'b0, ChipSelectID}; + 8'h14: Dout <= {28'b0, ChipSelectDef}; + 8'h18: Dout <= {30'b0, ChipSelectMode}; + 8'h28: Dout <= {8'b0, Delay0[15:8], 8'b0, Delay0[7:0]}; + 8'h2C: Dout <= {8'b0, Delay1[15:8], 8'b0, Delay1[7:0]}; + 8'h40: Dout <= {12'b0, Format[4:1], 13'b0, Format[0], 2'b0}; + 8'h48: Dout <= {23'b0, TransmitFIFOWriteFull, 8'b0}; + 8'h4C: Dout <= {23'b0, ReceiveFIFOReadEmpty, ReceiveData[7:0]}; + 8'h50: Dout <= {29'b0, TransmitWatermark}; + 8'h54: Dout <= {29'b0, ReceiveWatermark}; + 8'h70: Dout <= {30'b0, InterruptEnable}; + 8'h74: Dout <= {30'b0, InterruptPending}; + default: Dout <= 32'b0; endcase end @@ -200,7 +200,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) ( assign SCLKenable = (DivCounter == SckDiv); assign SCLKenableEarly = ((DivCounter + 12'b1) == SckDiv); always_ff @(posedge PCLK, negedge PRESETn) - if (~PRESETn) DivCounter <= #1 0; + if (~PRESETn) DivCounter <= 0; else if (SCLKenable) DivCounter <= 0; else DivCounter <= DivCounter + 12'b1; diff --git a/src/uncore/uartPC16550D.sv b/src/uncore/uartPC16550D.sv index f8aa4e016..4d6074dde 100644 --- a/src/uncore/uartPC16550D.sv +++ b/src/uncore/uartPC16550D.sv @@ -125,10 +125,10 @@ module uartPC16550D #(parameter UART_PRESCALE) ( /////////////////////////////////////////// always_ff @(posedge PCLK) begin - {SINd, DSRbd, DCDbd, CTSbd, RIbd} <= #1 {SIN, DSRb, DCDb, CTSb, RIb}; - {SINsync, DSRbsync, DCDbsync, CTSbsync, RIbsync} <= #1 loop ? {SOUTbit, ~MCR[0], ~MCR[3], ~MCR[1], ~MCR[2]} : + {SINd, DSRbd, DCDbd, CTSbd, RIbd} <= {SIN, DSRb, DCDb, CTSb, RIb}; + {SINsync, DSRbsync, DCDbsync, CTSbsync, RIbsync} <= loop ? {SOUTbit, ~MCR[0], ~MCR[3], ~MCR[1], ~MCR[2]} : {SINd, DSRbd, DCDbd, CTSbd, RIbd}; // syncrhonized signals, handle loopback testing - {DSRb2, DCDb2, CTSb2, RIb2} <= #1 {DSRbsync, DCDbsync, CTSbsync, RIbsync}; // for detecting state changes + {DSRb2, DCDb2, CTSb2, RIb2} <= {DSRbsync, DCDbsync, CTSbsync, RIbsync}; // for detecting state changes end /////////////////////////////////////////// @@ -137,25 +137,25 @@ module uartPC16550D #(parameter UART_PRESCALE) ( always_ff @(posedge PCLK, negedge PRESETn) if (~PRESETn) begin // Table 3 Reset Configuration - IER <= #1 4'b0; - FCR <= #1 8'b0; - LCR <= #1 8'b11; // **** fpga used to require reset to 3, double check this is no longer needed. - MCR <= #1 5'b0; - LSR <= #1 8'b01100000; - MSR <= #1 4'b0; - DLL <= #1 8'd1; // this cannot be zero with DLM also zer0. - DLM <= #1 8'b0; - SCR <= #1 8'b0; // not strictly necessary to reset + IER <= 4'b0; + FCR <= 8'b0; + LCR <= 8'b11; // **** fpga used to require reset to 3, double check this is no longer needed. + MCR <= 5'b0; + LSR <= 8'b01100000; + MSR <= 4'b0; + DLL <= 8'd1; // this cannot be zero with DLM also zer0. + DLM <= 8'b0; + SCR <= 8'b0; // not strictly necessary to reset end else begin if (~MEMWb) begin /* verilator lint_off CASEINCOMPLETE */ case (A) - 3'b000: if (DLAB) DLL <= #1 Din; // else TXHR <= #1 Din; // TX handled in TX register/FIFO section - 3'b001: if (DLAB) DLM <= #1 Din; else IER <= #1 Din[3:0]; - 3'b010: FCR <= #1 {Din[7:6], 2'b0, Din[3], 2'b0, Din[0]}; // Write only FIFO Control Register; 4:5 reserved and 2:1 self-clearing - 3'b011: LCR <= #1 Din; - 3'b100: MCR <= #1 Din[4:0]; - 3'b111: SCR <= #1 Din; + 3'b000: if (DLAB) DLL <= Din; // else TXHR <= Din; // TX handled in TX register/FIFO section + 3'b001: if (DLAB) DLM <= Din; else IER <= Din[3:0]; + 3'b010: FCR <= {Din[7:6], 2'b0, Din[3], 2'b0, Din[0]}; // Write only FIFO Control Register; 4:5 reserved and 2:1 self-clearing + 3'b011: LCR <= Din; + 3'b100: MCR <= Din[4:0]; + 3'b111: SCR <= Din; endcase /* verilator lint_on CASEINCOMPLETE */ end @@ -163,28 +163,28 @@ module uartPC16550D #(parameter UART_PRESCALE) ( // Line Status Register (8.6.3) // Ben 6/9/21 I don't like how this is a register. A lot of the individual bits have clocked components, so this just adds unecessary delay. if (~MEMWb & (A == 3'b101)) - LSR[6:1] <= #1 Din[6:1]; // recommended only for test, see 8.6.3 + LSR[6:1] <= Din[6:1]; // recommended only for test, see 8.6.3 else begin - LSR[0] <= #1 rxdataready; // Data ready - LSR[1] <= #1 (LSR[1] | RXBR[10]) & ~squashRXerrIP;; // overrun error - LSR[2] <= #1 (LSR[2] | RXBR[9]) & ~squashRXerrIP; // parity error - LSR[3] <= #1 (LSR[3] | RXBR[8]) & ~squashRXerrIP; // framing error - LSR[4] <= #1 (LSR[4] | rxbreak) & ~squashRXerrIP; // break indicator - LSR[5] <= #1 THRE; // THRE - LSR[6] <= #1 ~txsrfull & THRE; // TEMT - if (rxfifohaserr) LSR[7] <= #1 1; // any bits in FIFO have error + LSR[0] <= rxdataready; // Data ready + LSR[1] <= (LSR[1] | RXBR[10]) & ~squashRXerrIP;; // overrun error + LSR[2] <= (LSR[2] | RXBR[9]) & ~squashRXerrIP; // parity error + LSR[3] <= (LSR[3] | RXBR[8]) & ~squashRXerrIP; // framing error + LSR[4] <= (LSR[4] | rxbreak) & ~squashRXerrIP; // break indicator + LSR[5] <= THRE; // THRE + LSR[6] <= ~txsrfull & THRE; // TEMT + if (rxfifohaserr) LSR[7] <= 1; // any bits in FIFO have error end // Modem Status Register (8.6.8) if (~MEMWb & (A == 3'b110)) - MSR <= #1 Din[3:0]; + MSR <= Din[3:0]; else if (~MEMRb & (A == 3'b110)) - MSR <= #1 4'b0; // Reading MSR clears the flags in MSR bits 3:0 + MSR <= 4'b0; // Reading MSR clears the flags in MSR bits 3:0 else begin - MSR[0] <= #1 MSR[0] | CTSb2 ^ CTSbsync; // Delta Clear to Send - MSR[1] <= #1 MSR[1] | DSRb2 ^ DSRbsync; // Delta Data Set Ready - MSR[2] <= #1 MSR[2] | (~RIb2 & RIbsync); // Trailing Edge of Ring Indicator - MSR[3] <= #1 MSR[3] | DCDb2 ^ DCDbsync; // Delta Data Carrier Detect + MSR[0] <= MSR[0] | CTSb2 ^ CTSbsync; // Delta Clear to Send + MSR[1] <= MSR[1] | DSRb2 ^ DSRbsync; // Delta Data Set Ready + MSR[2] <= MSR[2] | (~RIb2 & RIbsync); // Trailing Edge of Ring Indicator + MSR[3] <= MSR[3] | DCDb2 ^ DCDbsync; // Delta Data Carrier Detect end end always_comb @@ -214,18 +214,18 @@ module uartPC16550D #(parameter UART_PRESCALE) ( /////////////////////////////////////////// always_ff @(posedge PCLK, negedge PRESETn) if (~PRESETn) begin - baudcount <= #1 1; - baudpulse <= #1 0; + baudcount <= 1; + baudpulse <= 0; end else if (~MEMWb & DLAB & (A == 3'b0 | A == 3'b1)) begin - baudcount <= #1 1; + baudcount <= 1; end else begin // the baudpulse is too long by 2 clock cycles. // This is cause baudpulse is registered adding 1 cycle and // baudcount is reset when baudcount equals the threshold {DLM, DLL, UART_PRESCALE} // rather than 1 less than that value. Alternatively the reset value could be 1 rather // than 0. - baudpulse <= #1 baudpulseComb; - baudcount <= #1 baudpulseComb ? 1 : baudcount +1; + baudpulse <= baudpulseComb; + baudcount <= baudpulseComb ? 1 : baudcount +1; end assign baudpulseComb = (baudcount == {DLM, DLL, {(UART_PRESCALE){1'b0}}}); @@ -240,27 +240,27 @@ module uartPC16550D #(parameter UART_PRESCALE) ( always_ff @(posedge PCLK, negedge PRESETn) if (~PRESETn) begin - rxoversampledcnt <= #1 0; - rxstate <= #1 UART_IDLE; - rxbitsreceived <= #1 0; - rxtimeoutcnt <= #1 0; + rxoversampledcnt <= 0; + rxstate <= UART_IDLE; + rxbitsreceived <= 0; + rxtimeoutcnt <= 0; end else begin if (rxstate == UART_IDLE & ~SINsync) begin // got start bit - rxstate <= #1 UART_ACTIVE; - rxoversampledcnt <= #1 0; - rxbitsreceived <= #1 0; - if (~rxfifotimeout) rxtimeoutcnt <= #1 0; // reset timeout when new character is arriving. Jacob Pease: Only if the timeout was not already reached. p.16 PC16550D.pdf + rxstate <= UART_ACTIVE; + rxoversampledcnt <= 0; + rxbitsreceived <= 0; + if (~rxfifotimeout) rxtimeoutcnt <= 0; // reset timeout when new character is arriving. Jacob Pease: Only if the timeout was not already reached. p.16 PC16550D.pdf end else if (rxbaudpulse & (rxstate == UART_ACTIVE)) begin - rxoversampledcnt <= #1 rxoversampledcnt + 1; // 16x oversampled counter - if (rxcentered) rxbitsreceived <= #1 rxbitsreceived + 1; - if (rxbitsreceived == rxbitsexpected) rxstate <= #1 UART_DONE; // pulse rxdone for a cycle + rxoversampledcnt <= rxoversampledcnt + 1; // 16x oversampled counter + if (rxcentered) rxbitsreceived <= rxbitsreceived + 1; + if (rxbitsreceived == rxbitsexpected) rxstate <= UART_DONE; // pulse rxdone for a cycle end else if (rxstate == UART_DONE | rxstate == UART_BREAK) begin - if (rxbreak & ~SINsync) rxstate <= #1 UART_BREAK; - else rxstate <= #1 UART_IDLE; + if (rxbreak & ~SINsync) rxstate <= UART_BREAK; + else rxstate <= UART_IDLE; end // timeout counting - if (~MEMRb & A == 3'b000 & ~DLAB) rxtimeoutcnt <= #1 0; // reset timeout on read - else if (fifoenabled & ~rxfifoempty & rxbaudpulse & ~rxfifotimeout) rxtimeoutcnt <= #1 rxtimeoutcnt+1; // may not be right + if (~MEMRb & A == 3'b000 & ~DLAB) rxtimeoutcnt <= 0; // reset timeout on read + else if (fifoenabled & ~rxfifoempty & rxbaudpulse & ~rxfifotimeout) rxtimeoutcnt <= rxtimeoutcnt+1; // may not be right end assign rxcentered = rxbaudpulse & (rxoversampledcnt == 4'b1000); // implies rxstate = UART_ACTIVE @@ -272,8 +272,8 @@ module uartPC16550D #(parameter UART_PRESCALE) ( /////////////////////////////////////////// always_ff @(posedge PCLK, negedge PRESETn) - if (~PRESETn) rxshiftreg <= #1 10'b0000000001; // initialize so that there is a valid stop bit - else if (rxcentered) rxshiftreg <= #1 {rxshiftreg[8:0], SINsync}; // capture bit + if (~PRESETn) rxshiftreg <= 10'b0000000001; // initialize so that there is a valid stop bit + else if (rxcentered) rxshiftreg <= {rxshiftreg[8:0], SINsync}; // capture bit assign rxparitybit = rxshiftreg[1]; // parity, if it exists, in bit 1 when all done assign rxstopbit = rxshiftreg[0]; always_comb @@ -295,32 +295,32 @@ module uartPC16550D #(parameter UART_PRESCALE) ( // receive FIFO and register always_ff @(posedge PCLK) if (~PRESETn) begin - rxfifohead <= #1 0; rxfifotail <= #1 0; rxdataready <= #1 0; RXBR <= #1 0; + rxfifohead <= 0; rxfifotail <= 0; rxdataready <= 0; RXBR <= 0; end else begin if (~MEMWb & (A == 3'b010) & Din[1]) begin - rxfifohead <= #1 0; rxfifotail <= #1 0; rxdataready <= #1 0; + rxfifohead <= 0; rxfifotail <= 0; rxdataready <= 0; end else if (rxstate == UART_DONE) begin - RXBR <= #1 {rxoverrunerr, rxparityerr, rxframingerr, rxdata}; // load recevive buffer register + RXBR <= {rxoverrunerr, rxparityerr, rxframingerr, rxdata}; // load recevive buffer register if (rxoverrunerr) $warning("UART RX Overrun Err\n"); if (rxparityerr) $warning("UART RX Parity Err\n"); if (rxframingerr) $warning("UART RX Framing Err\n"); if (fifoenabled) begin - rxfifo[rxfifohead] <= #1 {rxoverrunerr, rxparityerr, rxframingerr, rxdata}; - rxfifohead <= #1 rxfifohead + 1; + rxfifo[rxfifohead] <= {rxoverrunerr, rxparityerr, rxframingerr, rxdata}; + rxfifohead <= rxfifohead + 1; end - rxdataready <= #1 1; + rxdataready <= 1; end else if (~MEMRb & A == 3'b000 & ~DLAB) begin // reading RBR updates ready / pops fifo if (fifoenabled) begin - if (~rxfifoempty) rxfifotail <= #1 rxfifotail + 1; - // if (rxfifoempty) rxdataready <= #1 0; - if (rxfifoentries == 1) rxdataready <= #1 0; // When reading the last entry, data ready becomes zero + if (~rxfifoempty) rxfifotail <= rxfifotail + 1; + // if (rxfifoempty) rxdataready <= 0; + if (rxfifoentries == 1) rxdataready <= 0; // When reading the last entry, data ready becomes zero end else begin - rxdataready <= #1 0; - RXBR <= #1 {1'b0, RXBR[9:0]}; // Ben 31 March 2022: I added this so that rxoverrunerr permanently goes away upon reading RBR (when not in FIFO mode) + rxdataready <= 0; + RXBR <= {1'b0, RXBR[9:0]}; // Ben 31 March 2022: I added this so that rxoverrunerr permanently goes away upon reading RBR (when not in FIFO mode) end end else if (~MEMWb & A == 3'b010) // writes to FIFO Control Register if (Din[1] | ~Din[0]) begin // rx FIFO reset or FIFO disable clears FIFO contents - rxfifohead <= #1 0; rxfifotail <= #1 0; + rxfifohead <= 0; rxfifotail <= 0; end end @@ -354,9 +354,9 @@ module uartPC16550D #(parameter UART_PRESCALE) ( // receive buffer register and ready bit always_ff @(posedge PCLK, negedge PRESETn) // track rxrdy for DMA mode (FCR3 = FCR0 = 1) - if (~PRESETn) rxfifodmaready <= #1 0; - else if (rxfifotriggered | rxfifotimeout) rxfifodmaready <= #1 1; - else if (rxfifoempty) rxfifodmaready <= #1 0; + if (~PRESETn) rxfifodmaready <= 0; + else if (rxfifotriggered | rxfifotimeout) rxfifodmaready <= 1; + else if (rxfifoempty) rxfifodmaready <= 0; always_comb if (fifoenabled) begin @@ -375,21 +375,21 @@ module uartPC16550D #(parameter UART_PRESCALE) ( always_ff @(posedge PCLK, negedge PRESETn) if (~PRESETn) begin - txoversampledcnt <= #1 0; - txstate <= #1 UART_IDLE; - txbitssent <= #1 0; + txoversampledcnt <= 0; + txstate <= UART_IDLE; + txbitssent <= 0; end else if ((txstate == UART_IDLE) & txsrfull) begin // start transmitting - txstate <= #1 UART_ACTIVE; - txoversampledcnt <= #1 1; - txbitssent <= #1 0; + txstate <= UART_ACTIVE; + txoversampledcnt <= 1; + txbitssent <= 0; end else if (txbaudpulse & (txstate == UART_ACTIVE)) begin - txoversampledcnt <= #1 txoversampledcnt + 1; + txoversampledcnt <= txoversampledcnt + 1; if (txnextbit) begin // transmit at end of phase - txbitssent <= #1 txbitssent+1; - if (txbitssent == txbitsexpected) txstate <= #1 UART_DONE; + txbitssent <= txbitssent+1; + if (txbitssent == txbitsexpected) txstate <= UART_DONE; end end else if (txstate == UART_DONE) begin - txstate <= #1 UART_IDLE; + txstate <= UART_IDLE; end assign txbitsexpected = 4'd1 + (4'd5 + {2'b00, LCR[1:0]}) + {3'b000, LCR[3]} + 4'd1 + {3'b000, LCR[2]} - 4'd1; // start bit + data bits + (parity bit) + stop bit(s) - 1 @@ -423,37 +423,37 @@ module uartPC16550D #(parameter UART_PRESCALE) ( // registers & FIFO always_ff @(posedge PCLK, negedge PRESETn) if (~PRESETn) begin - txfifohead <= #1 0; txfifotail <= #1 0; txhrfull <= #1 0; txsrfull <= #1 0; TXHR <= #1 0; txsr <= #1 12'hfff; + txfifohead <= 0; txfifotail <= 0; txhrfull <= 0; txsrfull <= 0; TXHR <= 0; txsr <= 12'hfff; end else if (~MEMWb & (A == 3'b010) & Din[2]) begin - txfifohead <= #1 0; txfifotail <= #1 0; + txfifohead <= 0; txfifotail <= 0; end else begin if (~MEMWb & A == 3'b000 & ~DLAB) begin // writing transmit holding register or fifo if (fifoenabled) begin - txfifo[txfifohead] <= #1 Din; - txfifohead <= #1 txfifohead + 1; + txfifo[txfifohead] <= Din; + txfifohead <= txfifohead + 1; end else begin - TXHR <= #1 Din; - txhrfull <= #1 1; + TXHR <= Din; + txhrfull <= 1; end $write("%c",Din); // for testbench end if (txstate == UART_IDLE) begin // move data into tx shift register if available if (fifoenabled) begin if (~txfifoempty & ~txsrfull) begin - txsr <= #1 txdata; - txfifotail <= #1 txfifotail+1; - txsrfull <= #1 1; + txsr <= txdata; + txfifotail <= txfifotail+1; + txsrfull <= 1; end end else if (txhrfull) begin - txsr <= #1 txdata; - txhrfull <= #1 0; - txsrfull <= #1 1; + txsr <= txdata; + txhrfull <= 0; + txsrfull <= 1; end - end else if (txstate == UART_DONE) txsrfull <= #1 0; // done transmitting shift register - else if (txstate == UART_ACTIVE & txnextbit) txsr <= #1 {txsr[10:0], 1'b1}; // shift txhr + end else if (txstate == UART_DONE) txsrfull <= 0; // done transmitting shift register + else if (txstate == UART_ACTIVE & txnextbit) txsr <= {txsr[10:0], 1'b1}; // shift txhr if (!MEMWb & A == 3'b010) // writes to FIFO control register if (Din[2] | ~Din[0]) begin // tx FIFO reste or FIFO disable clears FIFO contents - txfifohead <= #1 0; txfifotail <= #1 0; + txfifohead <= 0; txfifotail <= 0; end end @@ -483,9 +483,9 @@ module uartPC16550D #(parameter UART_PRESCALE) ( // transmit buffer ready bit always_ff @(posedge PCLK, negedge PRESETn) // track txrdy for DMA mode (FCR3 = FCR0 = 1) - if (~PRESETn) txfifodmaready <= #1 0; - else if (txfifoempty) txfifodmaready <= #1 1; - else if (txfifofull) txfifodmaready <= #1 0; + if (~PRESETn) txfifodmaready <= 0; + else if (txfifoempty) txfifodmaready <= 1; + else if (txfifofull) txfifodmaready <= 0; always_comb if (fifoenabled & fifodmamodesel) TXRDYb = ~txfifodmaready; @@ -520,7 +520,7 @@ module uartPC16550D #(parameter UART_PRESCALE) ( intrpending = 0; end end - always @(posedge PCLK) INTR <= #1 intrpending; // prevent glitches on interrupt pin + always @(posedge PCLK) INTR <= intrpending; // prevent glitches on interrupt pin // Side effect of reading LSR is lowering overrun, parity, framing, break intr's assign setSquashRXerrIP = ~MEMRb & (A==3'b101); diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 746fde068..b1ea87eb1 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -283,7 +283,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign valid = InstrValidW & ~StallW; assign rvvi.clk = clk; - assign #1 rvvi.valid[0][0] = valid; + assign rvvi.valid[0][0] = valid; assign rvvi.order[0][0] = CSRArray[12'hB02]; // TODO: IMPERAS Should be event order assign rvvi.insn[0][0] = InstrRawW; assign rvvi.pc_rdata[0][0] = PCW; @@ -360,44 +360,44 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); end // check for csr value change. - assign #2 CSR_W[12'h300] = (CSRArrayOld[12'h300] != CSRArray[12'h300]) ? 1 : 0; - assign #2 CSR_W[12'h310] = (CSRArrayOld[12'h310] != CSRArray[12'h310]) ? 1 : 0; - assign #2 CSR_W[12'h305] = (CSRArrayOld[12'h305] != CSRArray[12'h305]) ? 1 : 0; - assign #2 CSR_W[12'h341] = (CSRArrayOld[12'h341] != CSRArray[12'h341]) ? 1 : 0; - assign #2 CSR_W[12'h306] = (CSRArrayOld[12'h306] != CSRArray[12'h306]) ? 1 : 0; - assign #2 CSR_W[12'h30A] = (CSRArrayOld[12'h30A] != CSRArray[12'h30A]) ? 1 : 0; - assign #2 CSR_W[12'h320] = (CSRArrayOld[12'h320] != CSRArray[12'h320]) ? 1 : 0; - assign #2 CSR_W[12'h302] = (CSRArrayOld[12'h302] != CSRArray[12'h302]) ? 1 : 0; - assign #2 CSR_W[12'h303] = (CSRArrayOld[12'h303] != CSRArray[12'h303]) ? 1 : 0; - assign #2 CSR_W[12'h344] = (CSRArrayOld[12'h344] != CSRArray[12'h344]) ? 1 : 0; - assign #2 CSR_W[12'h304] = (CSRArrayOld[12'h304] != CSRArray[12'h304]) ? 1 : 0; - assign #2 CSR_W[12'h301] = (CSRArrayOld[12'h301] != CSRArray[12'h301]) ? 1 : 0; - assign #2 CSR_W[12'hF14] = (CSRArrayOld[12'hF14] != CSRArray[12'hF14]) ? 1 : 0; - assign #2 CSR_W[12'h340] = (CSRArrayOld[12'h340] != CSRArray[12'h340]) ? 1 : 0; - assign #2 CSR_W[12'h342] = (CSRArrayOld[12'h342] != CSRArray[12'h342]) ? 1 : 0; - assign #2 CSR_W[12'h343] = (CSRArrayOld[12'h343] != CSRArray[12'h343]) ? 1 : 0; - assign #2 CSR_W[12'hF11] = (CSRArrayOld[12'hF11] != CSRArray[12'hF11]) ? 1 : 0; - assign #2 CSR_W[12'hF12] = (CSRArrayOld[12'hF12] != CSRArray[12'hF12]) ? 1 : 0; - assign #2 CSR_W[12'hF13] = (CSRArrayOld[12'hF13] != CSRArray[12'hF13]) ? 1 : 0; - assign #2 CSR_W[12'hF15] = (CSRArrayOld[12'hF15] != CSRArray[12'hF15]) ? 1 : 0; - assign #2 CSR_W[12'h34A] = (CSRArrayOld[12'h34A] != CSRArray[12'h34A]) ? 1 : 0; - assign #2 CSR_W[12'hB00] = (CSRArrayOld[12'hB00] != CSRArray[12'hB00]) ? 1 : 0; - assign #2 CSR_W[12'hB02] = (CSRArrayOld[12'hB02] != CSRArray[12'hB02]) ? 1 : 0; - assign #2 CSR_W[12'h100] = (CSRArrayOld[12'h100] != CSRArray[12'h100]) ? 1 : 0; - assign #2 CSR_W[12'h104] = (CSRArrayOld[12'h104] != CSRArray[12'h104]) ? 1 : 0; - assign #2 CSR_W[12'h105] = (CSRArrayOld[12'h105] != CSRArray[12'h105]) ? 1 : 0; - assign #2 CSR_W[12'h141] = (CSRArrayOld[12'h141] != CSRArray[12'h141]) ? 1 : 0; - assign #2 CSR_W[12'h106] = (CSRArrayOld[12'h106] != CSRArray[12'h106]) ? 1 : 0; - assign #2 CSR_W[12'h10A] = (CSRArrayOld[12'h10A] != CSRArray[12'h10A]) ? 1 : 0; - assign #2 CSR_W[12'h180] = (CSRArrayOld[12'h180] != CSRArray[12'h180]) ? 1 : 0; - assign #2 CSR_W[12'h140] = (CSRArrayOld[12'h140] != CSRArray[12'h140]) ? 1 : 0; - assign #2 CSR_W[12'h143] = (CSRArrayOld[12'h143] != CSRArray[12'h143]) ? 1 : 0; - assign #2 CSR_W[12'h142] = (CSRArrayOld[12'h142] != CSRArray[12'h142]) ? 1 : 0; - assign #2 CSR_W[12'h144] = (CSRArrayOld[12'h144] != CSRArray[12'h144]) ? 1 : 0; - assign #2 CSR_W[12'h14D] = (CSRArrayOld[12'h14D] != CSRArray[12'h14D]) ? 1 : 0; - assign #2 CSR_W[12'h001] = (CSRArrayOld[12'h001] != CSRArray[12'h001]) ? 1 : 0; - assign #2 CSR_W[12'h002] = (CSRArrayOld[12'h002] != CSRArray[12'h002]) ? 1 : 0; - assign #2 CSR_W[12'h003] = (CSRArrayOld[12'h003] != CSRArray[12'h003]) ? 1 : 0; + assign CSR_W[12'h300] = (CSRArrayOld[12'h300] != CSRArray[12'h300]) ? 1 : 0; + assign CSR_W[12'h310] = (CSRArrayOld[12'h310] != CSRArray[12'h310]) ? 1 : 0; + assign CSR_W[12'h305] = (CSRArrayOld[12'h305] != CSRArray[12'h305]) ? 1 : 0; + assign CSR_W[12'h341] = (CSRArrayOld[12'h341] != CSRArray[12'h341]) ? 1 : 0; + assign CSR_W[12'h306] = (CSRArrayOld[12'h306] != CSRArray[12'h306]) ? 1 : 0; + assign CSR_W[12'h30A] = (CSRArrayOld[12'h30A] != CSRArray[12'h30A]) ? 1 : 0; + assign CSR_W[12'h320] = (CSRArrayOld[12'h320] != CSRArray[12'h320]) ? 1 : 0; + assign CSR_W[12'h302] = (CSRArrayOld[12'h302] != CSRArray[12'h302]) ? 1 : 0; + assign CSR_W[12'h303] = (CSRArrayOld[12'h303] != CSRArray[12'h303]) ? 1 : 0; + assign CSR_W[12'h344] = (CSRArrayOld[12'h344] != CSRArray[12'h344]) ? 1 : 0; + assign CSR_W[12'h304] = (CSRArrayOld[12'h304] != CSRArray[12'h304]) ? 1 : 0; + assign CSR_W[12'h301] = (CSRArrayOld[12'h301] != CSRArray[12'h301]) ? 1 : 0; + assign CSR_W[12'hF14] = (CSRArrayOld[12'hF14] != CSRArray[12'hF14]) ? 1 : 0; + assign CSR_W[12'h340] = (CSRArrayOld[12'h340] != CSRArray[12'h340]) ? 1 : 0; + assign CSR_W[12'h342] = (CSRArrayOld[12'h342] != CSRArray[12'h342]) ? 1 : 0; + assign CSR_W[12'h343] = (CSRArrayOld[12'h343] != CSRArray[12'h343]) ? 1 : 0; + assign CSR_W[12'hF11] = (CSRArrayOld[12'hF11] != CSRArray[12'hF11]) ? 1 : 0; + assign CSR_W[12'hF12] = (CSRArrayOld[12'hF12] != CSRArray[12'hF12]) ? 1 : 0; + assign CSR_W[12'hF13] = (CSRArrayOld[12'hF13] != CSRArray[12'hF13]) ? 1 : 0; + assign CSR_W[12'hF15] = (CSRArrayOld[12'hF15] != CSRArray[12'hF15]) ? 1 : 0; + assign CSR_W[12'h34A] = (CSRArrayOld[12'h34A] != CSRArray[12'h34A]) ? 1 : 0; + assign CSR_W[12'hB00] = (CSRArrayOld[12'hB00] != CSRArray[12'hB00]) ? 1 : 0; + assign CSR_W[12'hB02] = (CSRArrayOld[12'hB02] != CSRArray[12'hB02]) ? 1 : 0; + assign CSR_W[12'h100] = (CSRArrayOld[12'h100] != CSRArray[12'h100]) ? 1 : 0; + assign CSR_W[12'h104] = (CSRArrayOld[12'h104] != CSRArray[12'h104]) ? 1 : 0; + assign CSR_W[12'h105] = (CSRArrayOld[12'h105] != CSRArray[12'h105]) ? 1 : 0; + assign CSR_W[12'h141] = (CSRArrayOld[12'h141] != CSRArray[12'h141]) ? 1 : 0; + assign CSR_W[12'h106] = (CSRArrayOld[12'h106] != CSRArray[12'h106]) ? 1 : 0; + assign CSR_W[12'h10A] = (CSRArrayOld[12'h10A] != CSRArray[12'h10A]) ? 1 : 0; + assign CSR_W[12'h180] = (CSRArrayOld[12'h180] != CSRArray[12'h180]) ? 1 : 0; + assign CSR_W[12'h140] = (CSRArrayOld[12'h140] != CSRArray[12'h140]) ? 1 : 0; + assign CSR_W[12'h143] = (CSRArrayOld[12'h143] != CSRArray[12'h143]) ? 1 : 0; + assign CSR_W[12'h142] = (CSRArrayOld[12'h142] != CSRArray[12'h142]) ? 1 : 0; + assign CSR_W[12'h144] = (CSRArrayOld[12'h144] != CSRArray[12'h144]) ? 1 : 0; + assign CSR_W[12'h14D] = (CSRArrayOld[12'h14D] != CSRArray[12'h14D]) ? 1 : 0; + assign CSR_W[12'h001] = (CSRArrayOld[12'h001] != CSRArray[12'h001]) ? 1 : 0; + assign CSR_W[12'h002] = (CSRArrayOld[12'h002] != CSRArray[12'h002]) ? 1 : 0; + assign CSR_W[12'h003] = (CSRArrayOld[12'h003] != CSRArray[12'h003]) ? 1 : 0; assign rvvi.csr_wb[0][0][12'h300] = CSR_W[12'h300]; assign rvvi.csr_wb[0][0][12'h310] = CSR_W[12'h310]; @@ -479,14 +479,14 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); // PMP CFG 3A0 to 3AF for(index='h3A0; index<='h3AF; index++) begin - assign #2 CSR_W[index] = (CSRArrayOld[index] != CSRArray[index]) ? 1 : 0; + assign CSR_W[index] = (CSRArrayOld[index] != CSRArray[index]) ? 1 : 0; assign rvvi.csr_wb[0][0][index] = CSR_W[index]; assign rvvi.csr[0][0][index] = CSRArray[index]; end // PMP ADDR 3B0 to 3EF for(index='h3B0; index<='h3EF; index++) begin - assign #2 CSR_W[index] = (CSRArrayOld[index] != CSRArray[index]) ? 1 : 0; + assign CSR_W[index] = (CSRArrayOld[index] != CSRArray[index]) ? 1 : 0; assign rvvi.csr_wb[0][0][index] = CSR_W[index]; assign rvvi.csr[0][0][index] = CSRArray[index]; end diff --git a/testbench/sdc/sdModel.sv b/testbench/sdc/sdModel.sv index f2a5127d8..aea247035 100644 --- a/testbench/sdc/sdModel.sv +++ b/testbench/sdc/sdModel.sv @@ -498,7 +498,7 @@ module sdModel crcRst<=0; crcIn <= #`tIH qCmd; // tIH 0 inCmd[47-cmdRead] <= #`tIH qCmd; // tIH 0 - cmdRead <= #1 cmdRead+1; + cmdRead <=cmdRead+1; if (cmdRead >= 40) crcEn<=0; From ac00eaf32284d8516eb47ba5a96c6627fb0741e2 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Wed, 20 Mar 2024 09:50:52 -0700 Subject: [PATCH 02/12] added some missing derived configs --- config/derivlist.txt | 269 +++++++++++++++++++++++++++++++++++++++++++ sim/regression-wally | 58 ++++------ 2 files changed, 293 insertions(+), 34 deletions(-) diff --git a/config/derivlist.txt b/config/derivlist.txt index 6851278b3..1c4f19fe2 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -616,6 +616,10 @@ deriv f_div_4_2_rv32gc div_4_2_rv32gc MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) ZFH_SUPPORTED 0 +deriv f_div_4_4_rv32gc div_4_4_rv32gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + deriv f_div_2_1_rv64gc div_2_1_rv64gc MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) ZFH_SUPPORTED 0 @@ -662,6 +666,10 @@ deriv fh_div_4_2_rv32gc div_4_2_rv32gc MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) ZFH_SUPPORTED 1 +deriv fh_div_4_4_rv32gc div_4_4_rv32gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + deriv fh_div_2_1_rv64gc div_2_1_rv64gc MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) ZFH_SUPPORTED 1 @@ -708,6 +716,10 @@ deriv fd_div_4_2_rv32gc div_4_2_rv32gc MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) ZFH_SUPPORTED 0 +deriv fd_div_4_4_rv32gc div_4_4_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + deriv fd_div_2_1_rv64gc div_2_1_rv64gc MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) ZFH_SUPPORTED 0 @@ -755,6 +767,10 @@ deriv fdh_div_4_2_rv32gc div_4_2_rv32gc MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) ZFH_SUPPORTED 1 +deriv fdh_div_4_4_rv32gc div_4_4_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + deriv fdh_div_2_1_rv64gc div_2_1_rv64gc MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) ZFH_SUPPORTED 1 @@ -801,6 +817,10 @@ deriv fdq_div_4_2_rv32gc div_4_2_rv32gc MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) ZFH_SUPPORTED 0 +deriv fdq_div_4_4_rv32gc div_4_4_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + deriv fdq_div_2_1_rv64gc div_2_1_rv64gc MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) ZFH_SUPPORTED 0 @@ -847,6 +867,10 @@ deriv fdqh_div_4_2_rv32gc div_4_2_rv32gc MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) ZFH_SUPPORTED 1 +deriv fdqh_div_4_4_rv32gc div_4_4_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + deriv fdqh_div_2_1_rv64gc div_2_1_rv64gc MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) ZFH_SUPPORTED 1 @@ -888,6 +912,9 @@ IEEE754 1 deriv f_ieee_div_4_2_rv32gc f_div_4_2_rv32gc IEEE754 1 +deriv f_ieee_div_4_4_rv32gc f_div_4_4_rv32gc +IEEE754 1 + deriv f_ieee_div_2_1_rv64gc f_div_2_1_rv64gc IEEE754 1 @@ -922,6 +949,9 @@ IEEE754 1 deriv fh_ieee_div_4_2_rv32gc fh_div_4_2_rv32gc IEEE754 1 +deriv fh_ieee_div_4_4_rv32gc fh_div_4_4_rv32gc +IEEE754 1 + deriv fh_ieee_div_2_1_rv64gc fh_div_2_1_rv64gc IEEE754 1 @@ -956,6 +986,9 @@ IEEE754 1 deriv fd_ieee_div_4_2_rv32gc fd_div_4_2_rv32gc IEEE754 1 +deriv fd_ieee_div_4_4_rv32gc fd_div_4_4_rv32gc +IEEE754 1 + deriv fd_ieee_div_2_1_rv64gc fd_div_2_1_rv64gc IEEE754 1 @@ -991,6 +1024,9 @@ IEEE754 1 deriv fdh_ieee_div_4_2_rv32gc fdh_div_4_2_rv32gc IEEE754 1 +deriv fdh_ieee_div_4_4_rv32gc fdh_div_4_4_rv32gc +IEEE754 1 + deriv fdh_ieee_div_2_1_rv64gc fdh_div_2_1_rv64gc IEEE754 1 @@ -1025,6 +1061,9 @@ IEEE754 1 deriv fdq_ieee_div_4_2_rv32gc fdq_div_4_2_rv32gc IEEE754 1 +deriv fdq_ieee_div_4_4_rv32gc fdq_div_4_4_rv32gc +IEEE754 1 + deriv fdq_ieee_div_2_1_rv64gc fdq_div_2_1_rv64gc IEEE754 1 @@ -1060,6 +1099,9 @@ IEEE754 1 deriv fdqh_ieee_div_4_2_rv32gc fdqh_div_4_2_rv32gc IEEE754 1 +deriv fdqh_ieee_div_4_4_rv32gc fdqh_div_4_4_rv32gc +IEEE754 1 + deriv fdqh_ieee_div_2_1_rv64gc fdqh_div_2_1_rv64gc IEEE754 1 @@ -1078,4 +1120,231 @@ IEEE754 1 deriv fdqh_ieee_div_4_4_rv64gc fdqh_div_4_4_rv64gc IEEE754 1 +#### DIVIDER VARIANTS WITH IDIV ON FPU + +deriv f_ieee_div_2_1i_rv32gc f_ieee_div_2_1_rv32gc +IDIV_ON_FPU 1 + +deriv f_ieee_div_2_2i_rv32gc f_ieee_div_2_2_rv32gc +IDIV_ON_FPU 1 + +deriv f_ieee_div_2_4i_rv32gc f_ieee_div_2_4_rv32gc +IDIV_ON_FPU 1 + +deriv f_ieee_div_4_1i_rv32gc f_ieee_div_4_1_rv32gc +IDIV_ON_FPU 1 + +deriv f_ieee_div_4_2i_rv32gc f_ieee_div_4_2_rv32gc +IDIV_ON_FPU 1 + +deriv f_ieee_div_4_4i_rv32gc f_ieee_div_4_4_rv32gc +IDIV_ON_FPU 1 + +deriv f_ieee_div_2_1i_rv64gc f_ieee_div_2_1_rv64gc +IDIV_ON_FPU 1 + +deriv f_ieee_div_2_2i_rv64gc f_ieee_div_2_2_rv64gc +IDIV_ON_FPU 1 + +deriv f_ieee_div_2_4i_rv64gc f_ieee_div_2_4_rv64gc +IDIV_ON_FPU 1 + +deriv f_ieee_div_4_1i_rv64gc f_ieee_div_4_1_rv64gc +IDIV_ON_FPU 1 + +deriv f_ieee_div_4_2i_rv64gc f_ieee_div_4_2_rv64gc +IDIV_ON_FPU 1 + +deriv f_ieee_div_4_4i_rv64gc f_ieee_div_4_4_rv64gc +IDIV_ON_FPU 1 + +#### FH_only, RK variable +deriv fh_ieee_div_2_1i_rv32gc fh_ieee_div_2_1_rv32gc +IDIV_ON_FPU 1 + +deriv fh_ieee_div_2_2i_rv32gc fh_ieee_div_2_2_rv32gc +IDIV_ON_FPU 1 + +deriv fh_ieee_div_2_4i_rv32gc fh_ieee_div_2_4_rv32gc +IDIV_ON_FPU 1 + +deriv fh_ieee_div_4_1i_rv32gc fh_ieee_div_4_1_rv32gc +IDIV_ON_FPU 1 + +deriv fh_ieee_div_4_2i_rv32gc fh_ieee_div_4_2_rv32gc +IDIV_ON_FPU 1 + +deriv fh_ieee_div_4_4i_rv32gc fh_ieee_div_4_4_rv32gc +IDIV_ON_FPU 1 + +deriv fh_ieee_div_2_1i_rv64gc fh_ieee_div_2_1_rv64gc +IDIV_ON_FPU 1 + +deriv fh_ieee_div_2_2i_rv64gc fh_ieee_div_2_2_rv64gc +IDIV_ON_FPU 1 + +deriv fh_ieee_div_2_4i_rv64gc fh_ieee_div_2_4_rv64gc +IDIV_ON_FPU 1 + +deriv fh_ieee_div_4_1i_rv64gc fh_ieee_div_4_1_rv64gc +IDIV_ON_FPU 1 + +deriv fh_ieee_div_4_2i_rv64gc fh_ieee_div_4_2_rv64gc +IDIV_ON_FPU 1 + +deriv fh_ieee_div_4_4i_rv64gc fh_ieee_div_4_4_rv64gc +IDIV_ON_FPU 1 + +# FD only , rk variable + +deriv fd_ieee_div_2_1i_rv32gc fd_ieee_div_2_1_rv32gc +IDIV_ON_FPU 1 + +deriv fd_ieee_div_2_2i_rv32gc fd_ieee_div_2_2_rv32gc +IDIV_ON_FPU 1 + +deriv fd_ieee_div_2_4i_rv32gc fd_ieee_div_2_4_rv32gc +IDIV_ON_FPU 1 + +deriv fd_ieee_div_4_1i_rv32gc fd_ieee_div_4_1_rv32gc +IDIV_ON_FPU 1 + +deriv fd_ieee_div_4_2i_rv32gc fd_ieee_div_4_2_rv32gc +IDIV_ON_FPU 1 + +deriv fd_ieee_div_4_4i_rv32gc fd_ieee_div_4_4_rv32gc +IDIV_ON_FPU 1 + +deriv fd_ieee_div_2_1i_rv64gc fd_ieee_div_2_1_rv64gc +IDIV_ON_FPU 1 + +deriv fd_ieee_div_2_2i_rv64gc fd_ieee_div_2_2_rv64gc +IDIV_ON_FPU 1 + +deriv fd_ieee_div_2_4i_rv64gc fd_ieee_div_2_4_rv64gc +IDIV_ON_FPU 1 + +deriv fd_ieee_div_4_1i_rv64gc fd_ieee_div_4_1_rv64gc +IDIV_ON_FPU 1 + +deriv fd_ieee_div_4_2i_rv64gc fd_ieee_div_4_2_rv64gc +IDIV_ON_FPU 1 + +deriv fd_ieee_div_4_4i_rv64gc fd_ieee_div_4_4_rv64gc +IDIV_ON_FPU 1 + +# FDH only , rk variable + +deriv fdh_ieee_div_2_1i_rv32gc fdh_ieee_div_2_1_rv32gc +IDIV_ON_FPU 1 + +deriv fdh_ieee_div_2_2i_rv32gc fdh_ieee_div_2_2_rv32gc +IDIV_ON_FPU 1 + +deriv fdh_ieee_div_2_4i_rv32gc fdh_ieee_div_2_4_rv32gc +IDIV_ON_FPU 1 + +deriv fdh_ieee_div_4_1i_rv32gc fdh_ieee_div_4_1_rv32gc +IDIV_ON_FPU 1 + +deriv fdh_ieee_div_4_2i_rv32gc fdh_ieee_div_4_2_rv32gc +IDIV_ON_FPU 1 + +deriv fdh_ieee_div_4_4i_rv32gc fdh_ieee_div_4_4_rv32gc +IDIV_ON_FPU 1 + +deriv fdh_ieee_div_2_1i_rv64gc fdh_ieee_div_2_1_rv64gc +IDIV_ON_FPU 1 + +deriv fdh_ieee_div_2_2i_rv64gc fdh_ieee_div_2_2_rv64gc +IDIV_ON_FPU 1 + +deriv fdh_ieee_div_2_4i_rv64gc fdh_ieee_div_2_4_rv64gc +IDIV_ON_FPU 1 + +deriv fdh_ieee_div_4_1i_rv64gc fdh_ieee_div_4_1_rv64gc +IDIV_ON_FPU 1 + +deriv fdh_ieee_div_4_2i_rv64gc fdh_ieee_div_4_2_rv64gc +IDIV_ON_FPU 1 + +deriv fdh_ieee_div_4_4i_rv64gc fdh_ieee_div_4_4_rv64gc +IDIV_ON_FPU 1 + +# FDQ only , rk variable + +deriv fdq_ieee_div_2_1i_rv32gc fdq_ieee_div_2_1_rv32gc +IDIV_ON_FPU 1 + +deriv fdq_ieee_div_2_2i_rv32gc fdq_ieee_div_2_2_rv32gc +IDIV_ON_FPU 1 + +deriv fdq_ieee_div_2_4i_rv32gc fdq_ieee_div_2_4_rv32gc +IDIV_ON_FPU 1 + +deriv fdq_ieee_div_4_1i_rv32gc fdq_ieee_div_4_1_rv32gc +IDIV_ON_FPU 1 + +deriv fdq_ieee_div_4_2i_rv32gc fdq_ieee_div_4_2_rv32gc +IDIV_ON_FPU 1 + +deriv fdq_ieee_div_4_4i_rv32gc fdq_ieee_div_4_4_rv32gc +IDIV_ON_FPU 1 + +deriv fdq_ieee_div_2_1i_rv64gc fdq_ieee_div_2_1_rv64gc +IDIV_ON_FPU 1 + +deriv fdq_ieee_div_2_2i_rv64gc fdq_ieee_div_2_2_rv64gc +IDIV_ON_FPU 1 + +deriv fdq_ieee_div_2_4i_rv64gc fdq_ieee_div_2_4_rv64gc +IDIV_ON_FPU 1 + +deriv fdq_ieee_div_4_1i_rv64gc fdq_ieee_div_4_1_rv64gc +IDIV_ON_FPU 1 + +deriv fdq_ieee_div_4_2i_rv64gc fdq_ieee_div_4_2_rv64gc +IDIV_ON_FPU 1 + +deriv fdq_ieee_div_4_4i_rv64gc fdq_ieee_div_4_4_rv64gc +IDIV_ON_FPU 1 + +# FDQH only , rk variable + +deriv fdqh_ieee_div_2_1i_rv32gc fdqh_ieee_div_2_1_rv32gc +IDIV_ON_FPU 1 + +deriv fdqh_ieee_div_2_2i_rv32gc fdqh_ieee_div_2_2_rv32gc +IDIV_ON_FPU 1 + +deriv fdqh_ieee_div_2_4i_rv32gc fdqh_ieee_div_2_4_rv32gc +IDIV_ON_FPU 1 + +deriv fdqh_ieee_div_4_1i_rv32gc fdqh_ieee_div_4_1_rv32gc +IDIV_ON_FPU 1 + +deriv fdqh_ieee_div_4_2i_rv32gc fdqh_ieee_div_4_2_rv32gc +IDIV_ON_FPU 1 + +deriv fdqh_ieee_div_4_4i_rv32gc fdqh_ieee_div_4_4_rv32gc +IDIV_ON_FPU 1 + +deriv fdqh_ieee_div_2_1i_rv64gc fdqh_ieee_div_2_1_rv64gc +IDIV_ON_FPU 1 + +deriv fdqh_ieee_div_2_2i_rv64gc fdqh_ieee_div_2_2_rv64gc +IDIV_ON_FPU 1 + +deriv fdqh_ieee_div_2_4i_rv64gc fdqh_ieee_div_2_4_rv64gc +IDIV_ON_FPU 1 + +deriv fdqh_ieee_div_4_1i_rv64gc fdqh_ieee_div_4_1_rv64gc +IDIV_ON_FPU 1 + +deriv fdqh_ieee_div_4_2i_rv64gc fdqh_ieee_div_4_2_rv64gc +IDIV_ON_FPU 1 + +deriv fdqh_ieee_div_4_4i_rv64gc fdqh_ieee_div_4_4_rv64gc +IDIV_ON_FPU 1 + diff --git a/sim/regression-wally b/sim/regression-wally index 42c54d016..7c940f82b 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -313,40 +313,30 @@ for test in tests32e: # softfloat tests if (softfloat): configs = [] - softfloatconfigs = ['fdh_ieee_rv32gc', 'fdqh_ieee_rv32gc', 'fdq_ieee_rv32gc', \ - 'fh_ieee_v32gc', 'f_ieee_rv64gc', 'fdqh_ieee_rv64gc', \ - 'fdq_ieee_rv64gc', 'div_2_1_rv32gc', 'div_2_2_rv32gc', \ - 'div_2_4_rv32gc', 'div_4_1_rv32gc', 'div_4_2_rv32gc', \ - 'div_4_4_rv32gc', 'fd_ieee_rv32gc', 'fh_ieee_rv32gc', \ - 'div_2_1_rv64gc', 'div_2_2_rv64gc', 'div_2_4_rv64gc', \ - 'div_4_1_rv64gc', 'div_4_2_rv64gc', 'div_4_4_rv64gc', \ - 'fd_ieee_rv64gc', 'fh_ieee_rv64gc', 'f_ieee_rv32gc'] - softfloatconfigs = ['fdh_ieee_div_2_1_rv32gc', 'fdh_ieee_div_2_1_rv64gc', \ - 'fdh_ieee_div_2_2_rv32gc', 'fdh_ieee_div_2_2_rv64gc', 'fdh_ieee_div_2_4_rv32gc', \ - 'fdh_ieee_div_2_4_rv64gc', 'fdh_ieee_div_4_1_rv32gc', 'fdh_ieee_div_4_1_rv64gc', \ - 'fdh_ieee_div_4_2_rv32gc', 'fdh_ieee_div_4_2_rv64gc', 'fdh_ieee_div_4_4_rv64gc', \ - 'fdh_ieee_rv32gc', 'fd_ieee_div_2_1_rv32gc', 'fd_ieee_div_2_1_rv64gc', \ - 'fd_ieee_div_2_2_rv32gc', 'fd_ieee_div_2_2_rv64gc', 'fd_ieee_div_2_4_rv32gc', \ - 'fd_ieee_div_2_4_rv64gc', 'fd_ieee_div_4_1_rv32gc', 'fd_ieee_div_4_1_rv64gc', \ - 'fd_ieee_div_4_2_rv32gc', 'fd_ieee_div_4_2_rv64gc', 'fd_ieee_div_4_4_rv64gc', \ - 'fd_ieee_rv32gc', 'fd_ieee_rv64gc', 'fdqh_ieee_div_2_1_rv32gc', \ - 'fdqh_ieee_div_2_1_rv64gc', 'fdqh_ieee_div_2_2_rv32gc', 'fdqh_ieee_div_2_2_rv64gc', \ - 'fdqh_ieee_div_2_4_rv32gc', 'fdqh_ieee_div_2_4_rv64gc', 'fdqh_ieee_div_4_1_rv32gc', \ - 'fdqh_ieee_div_4_1_rv64gc', 'fdqh_ieee_div_4_2_rv32gc', 'fdqh_ieee_div_4_2_rv64gc',\ - 'fdqh_ieee_div_4_4_rv64gc', 'fdqh_ieee_rv32gc', 'fdqh_ieee_rv64gc', \ - 'fdq_ieee_div_2_1_rv32gc', 'fdq_ieee_div_2_1_rv64gc', 'fdq_ieee_div_2_2_rv32gc',\ - 'fdq_ieee_div_2_2_rv64gc', 'fdq_ieee_div_2_4_rv32gc', 'fdq_ieee_div_2_4_rv64gc', \ - 'fdq_ieee_div_4_1_rv32gc', 'fdq_ieee_div_4_1_rv64gc', 'fdq_ieee_div_4_2_rv32gc', \ - 'fdq_ieee_div_4_2_rv64gc', 'fdq_ieee_div_4_4_rv64gc', 'fdq_ieee_rv32gc', \ - 'fdq_ieee_rv64gc', 'fh_ieee_div_2_1_rv32gc', 'fh_ieee_div_2_1_rv64gc', \ - 'fh_ieee_div_2_2_rv32gc', 'fh_ieee_div_2_2_rv64gc', 'fh_ieee_div_2_4_rv32gc',\ - 'fh_ieee_div_2_4_rv64gc', 'fh_ieee_div_4_1_rv32gc', 'fh_ieee_div_4_1_rv64gc',\ - 'fh_ieee_div_4_2_rv32gc', 'fh_ieee_div_4_2_rv64gc', 'fh_ieee_div_4_4_rv64gc', \ - 'fh_ieee_rv32gc', 'fh_ieee_rv64gc', 'fh_ieee_v32gc', 'f_ieee_div_2_1_rv32gc', \ - 'f_ieee_div_2_1_rv64gc', 'f_ieee_div_2_2_rv32gc', 'f_ieee_div_2_2_rv64gc', \ - 'f_ieee_div_2_4_rv32gc', 'f_ieee_div_2_4_rv64gc', 'f_ieee_div_4_1_rv32gc', \ - 'f_ieee_div_4_1_rv64gc', 'f_ieee_div_4_2_rv32gc', 'f_ieee_div_4_2_rv64gc', \ - 'f_ieee_div_4_4_rv64gc', 'f_ieee_rv32gc', 'f_ieee_rv64gc'] + softfloatconfigs = [ + "fdh_ieee_div_2_1_rv32gc", "fdh_ieee_div_2_1_rv64gc", "fdh_ieee_div_2_2_rv32gc", + "fdh_ieee_div_2_2_rv64gc", "fdh_ieee_div_2_4_rv32gc", "fdh_ieee_div_2_4_rv64gc", + "fdh_ieee_div_4_1_rv32gc", "fdh_ieee_div_4_1_rv64gc", "fdh_ieee_div_4_2_rv32gc", + "fdh_ieee_div_4_2_rv64gc", "fdh_ieee_div_4_4_rv64gc", "fd_ieee_div_2_1_rv32gc", + "fd_ieee_div_2_1_rv64gc", "fd_ieee_div_2_2_rv32gc", "fd_ieee_div_2_2_rv64gc", + "fd_ieee_div_2_4_rv32gc", "fd_ieee_div_2_4_rv64gc", "fd_ieee_div_4_1_rv32gc", + "fd_ieee_div_4_1_rv64gc", "fd_ieee_div_4_2_rv32gc", "fd_ieee_div_4_2_rv64gc", + "fd_ieee_div_4_4_rv64gc", "fdqh_ieee_div_2_1_rv32gc", "fdqh_ieee_div_2_1_rv64gc", + "fdqh_ieee_div_2_2_rv32gc", "fdqh_ieee_div_2_2_rv64gc", "fdqh_ieee_div_2_4_rv32gc", + "fdqh_ieee_div_2_4_rv64gc", "fdqh_ieee_div_4_1_rv32gc", "fdqh_ieee_div_4_1_rv64gc", + "fdqh_ieee_div_4_2_rv32gc", "fdqh_ieee_div_4_2_rv64gc", "fdqh_ieee_div_4_4_rv64gc", + "fdq_ieee_div_2_1_rv32gc", "fdq_ieee_div_2_1_rv64gc", "fdq_ieee_div_2_2_rv32gc", + "fdq_ieee_div_2_2_rv64gc", "fdq_ieee_div_2_4_rv32gc", "fdq_ieee_div_2_4_rv64gc", + "fdq_ieee_div_4_1_rv32gc", "fdq_ieee_div_4_1_rv64gc", "fdq_ieee_div_4_2_rv32gc", + "fdq_ieee_div_4_2_rv64gc", "fdq_ieee_div_4_4_rv64gc", "fh_ieee_div_2_1_rv32gc", + "fh_ieee_div_2_1_rv64gc", "fh_ieee_div_2_2_rv32gc", "fh_ieee_div_2_2_rv64gc", + "fh_ieee_div_2_4_rv32gc", "fh_ieee_div_2_4_rv64gc", "fh_ieee_div_4_1_rv32gc", + "fh_ieee_div_4_1_rv64gc", "fh_ieee_div_4_2_rv32gc", "fh_ieee_div_4_2_rv64gc", + "fh_ieee_div_4_4_rv64gc", "f_ieee_div_2_1_rv32gc", "f_ieee_div_2_1_rv64gc", + "f_ieee_div_2_2_rv32gc", "f_ieee_div_2_2_rv64gc", "f_ieee_div_2_4_rv32gc", + "f_ieee_div_2_4_rv64gc", "f_ieee_div_4_1_rv32gc", "f_ieee_div_4_1_rv64gc", + "f_ieee_div_4_2_rv32gc", "f_ieee_div_4_2_rv64gc", "f_ieee_div_4_4_rv64gc" + ] for config in softfloatconfigs: # div test case divtest = TestCase( From c8b84ebbc5723c3ca25e4f97f4ca082b312a6d42 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Wed, 20 Mar 2024 09:58:14 -0700 Subject: [PATCH 03/12] regression-wally -softfloat with updated derived configs --- sim/regression-wally | 34 ++++++++++++++++++---------------- 1 file changed, 18 insertions(+), 16 deletions(-) diff --git a/sim/regression-wally b/sim/regression-wally index 4c5286886..f58c8bdfe 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -313,25 +313,27 @@ if (softfloat): "fdh_ieee_div_2_1_rv32gc", "fdh_ieee_div_2_1_rv64gc", "fdh_ieee_div_2_2_rv32gc", "fdh_ieee_div_2_2_rv64gc", "fdh_ieee_div_2_4_rv32gc", "fdh_ieee_div_2_4_rv64gc", "fdh_ieee_div_4_1_rv32gc", "fdh_ieee_div_4_1_rv64gc", "fdh_ieee_div_4_2_rv32gc", - "fdh_ieee_div_4_2_rv64gc", "fdh_ieee_div_4_4_rv64gc", "fd_ieee_div_2_1_rv32gc", - "fd_ieee_div_2_1_rv64gc", "fd_ieee_div_2_2_rv32gc", "fd_ieee_div_2_2_rv64gc", - "fd_ieee_div_2_4_rv32gc", "fd_ieee_div_2_4_rv64gc", "fd_ieee_div_4_1_rv32gc", - "fd_ieee_div_4_1_rv64gc", "fd_ieee_div_4_2_rv32gc", "fd_ieee_div_4_2_rv64gc", - "fd_ieee_div_4_4_rv64gc", "fdqh_ieee_div_2_1_rv32gc", "fdqh_ieee_div_2_1_rv64gc", - "fdqh_ieee_div_2_2_rv32gc", "fdqh_ieee_div_2_2_rv64gc", "fdqh_ieee_div_2_4_rv32gc", - "fdqh_ieee_div_2_4_rv64gc", "fdqh_ieee_div_4_1_rv32gc", "fdqh_ieee_div_4_1_rv64gc", - "fdqh_ieee_div_4_2_rv32gc", "fdqh_ieee_div_4_2_rv64gc", "fdqh_ieee_div_4_4_rv64gc", + "fdh_ieee_div_4_2_rv64gc", "fdh_ieee_div_4_4_rv32gc", "fdh_ieee_div_4_4_rv64gc", + "fd_ieee_div_2_1_rv32gc", "fd_ieee_div_2_1_rv64gc", "fd_ieee_div_2_2_rv32gc", + "fd_ieee_div_2_2_rv64gc", "fd_ieee_div_2_4_rv32gc", "fd_ieee_div_2_4_rv64gc", + "fd_ieee_div_4_1_rv32gc", "fd_ieee_div_4_1_rv64gc", "fd_ieee_div_4_2_rv32gc", + "fd_ieee_div_4_2_rv64gc", "fd_ieee_div_4_4_rv32gc", "fd_ieee_div_4_4_rv64gc", + "fdqh_ieee_div_2_1_rv32gc", "fdqh_ieee_div_2_1_rv64gc", "fdqh_ieee_div_2_2_rv32gc", + "fdqh_ieee_div_2_2_rv64gc", "fdqh_ieee_div_2_4_rv32gc", "fdqh_ieee_div_2_4_rv64gc", + "fdqh_ieee_div_4_1_rv32gc", "fdqh_ieee_div_4_1_rv64gc", "fdqh_ieee_div_4_2_rv32gc", + "fdqh_ieee_div_4_2_rv64gc", "fdqh_ieee_div_4_4_rv32gc", "fdqh_ieee_div_4_4_rv64gc", "fdq_ieee_div_2_1_rv32gc", "fdq_ieee_div_2_1_rv64gc", "fdq_ieee_div_2_2_rv32gc", "fdq_ieee_div_2_2_rv64gc", "fdq_ieee_div_2_4_rv32gc", "fdq_ieee_div_2_4_rv64gc", "fdq_ieee_div_4_1_rv32gc", "fdq_ieee_div_4_1_rv64gc", "fdq_ieee_div_4_2_rv32gc", - "fdq_ieee_div_4_2_rv64gc", "fdq_ieee_div_4_4_rv64gc", "fh_ieee_div_2_1_rv32gc", - "fh_ieee_div_2_1_rv64gc", "fh_ieee_div_2_2_rv32gc", "fh_ieee_div_2_2_rv64gc", - "fh_ieee_div_2_4_rv32gc", "fh_ieee_div_2_4_rv64gc", "fh_ieee_div_4_1_rv32gc", - "fh_ieee_div_4_1_rv64gc", "fh_ieee_div_4_2_rv32gc", "fh_ieee_div_4_2_rv64gc", - "fh_ieee_div_4_4_rv64gc", "f_ieee_div_2_1_rv32gc", "f_ieee_div_2_1_rv64gc", - "f_ieee_div_2_2_rv32gc", "f_ieee_div_2_2_rv64gc", "f_ieee_div_2_4_rv32gc", - "f_ieee_div_2_4_rv64gc", "f_ieee_div_4_1_rv32gc", "f_ieee_div_4_1_rv64gc", - "f_ieee_div_4_2_rv32gc", "f_ieee_div_4_2_rv64gc", "f_ieee_div_4_4_rv64gc" + "fdq_ieee_div_4_2_rv64gc", "fdq_ieee_div_4_4_rv32gc", "fdq_ieee_div_4_4_rv64gc", + "fh_ieee_div_2_1_rv32gc", "fh_ieee_div_2_1_rv64gc", "fh_ieee_div_2_2_rv32gc", + "fh_ieee_div_2_2_rv64gc", "fh_ieee_div_2_4_rv32gc", "fh_ieee_div_2_4_rv64gc", + "fh_ieee_div_4_1_rv32gc", "fh_ieee_div_4_1_rv64gc", "fh_ieee_div_4_2_rv32gc", + "fh_ieee_div_4_2_rv64gc", "fh_ieee_div_4_4_rv32gc", "fh_ieee_div_4_4_rv64gc", + "f_ieee_div_2_1_rv32gc", "f_ieee_div_2_1_rv64gc", "f_ieee_div_2_2_rv32gc", + "f_ieee_div_2_2_rv64gc", "f_ieee_div_2_4_rv32gc", "f_ieee_div_2_4_rv64gc", + "f_ieee_div_4_1_rv32gc", "f_ieee_div_4_1_rv64gc", "f_ieee_div_4_2_rv32gc", + "f_ieee_div_4_2_rv64gc", "f_ieee_div_4_4_rv32gc", "f_ieee_div_4_4_rv64gc" ] for config in softfloatconfigs: # div test case From 984ed42f6acdd5917e8c4331cc3dcdf10345b5d1 Mon Sep 17 00:00:00 2001 From: Shreesh Kulkarni Date: Fri, 22 Mar 2024 23:05:24 +0530 Subject: [PATCH 04/12] Patched coremark_sweep.py. The script now runs for both 32 and 64bit. --- benchmarks/coremark/coremark_sweep.py | 51 ++++++++++++++++----------- 1 file changed, 30 insertions(+), 21 deletions(-) diff --git a/benchmarks/coremark/coremark_sweep.py b/benchmarks/coremark/coremark_sweep.py index 14fa3064a..f725ad266 100644 --- a/benchmarks/coremark/coremark_sweep.py +++ b/benchmarks/coremark/coremark_sweep.py @@ -3,8 +3,8 @@ ## Written: Shreesh Kulkarni, kshreesh5@gmail.com ## Created: 20 March 2024 -## Modified: 20 March 2024 -## Purpose: Wally 32-bit Coremark sweep Script +## Modified: 22 March 2024 +## Purpose: Wally Coremark sweep Script for both 32 and 64 bit configs. ## Documentation: @@ -29,10 +29,9 @@ import os -import subprocess # normal os.system() doesn't seem to work. Tried subprocess and it works. - -# list of architectures to run. I have included only 32-bit for now as I'm still testing this script and modifying it to make it more efficient -arch_list = [ +import re +# list of architectures to run. +arch32_list = [ "rv32gc_zba_zbb_zbc", "rv32im_zicsr_zba_zbb_zbc", "rv32gc", @@ -40,22 +39,32 @@ arch_list = [ "rv32im_zicsr", "rv32i_zicsr" ] +arch64_list = [ + "rv64gc_zba_zbb_zbc", + "rv64im_zicsr_zba_zbb_zbc", + "rv64gc", + "rv64imc_zicsr", + "rv64im_zicsr", + "rv64i_zicsr" +] +xlen_values = ['32','64'] +for xlen_value in xlen_values: + if(xlen_value=='32'): + for arch in arch32_list: + os.system("make clean") + make_all = f"make all XLEN={xlen_value} ARCH={arch}" + os.system(make_all) + make_run = f"make run XLEN={xlen_value} ARCH={arch}" + os.system(make_run) + else: + for arch in arch64_list: + os.system("make clean") + make_all = f"make all XLEN={xlen_value} ARCH={arch}" + os.system(make_all) + make_run = f"make run XLEN={xlen_value} ARCH={arch}" + os.system(make_run) + -# make command. If we wish to run the remaining commands like make clean, need to maintain a separate list. -make_cmd = ["make", "run"] -# Iterate over the architectures -for arch in arch_list: - # Setting the arch variable - env = os.environ.copy() - env["ARCH"] = arch - # used subprocess to run coremark for each architecture - print(f"Running for architecture: {arch}") - result = subprocess.run(make_cmd, env=env, stdout=subprocess.PIPE, stderr=subprocess.PIPE, universal_newlines=True) - # diplay the output on console. If we wish to store the results in a file,need to write some file handling code. Review needed - print(result.stdout) - print(result.stderr) - print("\n" *5) - From 9976f7e617cbf07419533f73a4b7b3d58b1e15d8 Mon Sep 17 00:00:00 2001 From: Shreesh Kulkarni Date: Fri, 22 Mar 2024 23:09:14 +0530 Subject: [PATCH 05/12] Update coremark_sweep.py --- benchmarks/coremark/coremark_sweep.py | 1 - 1 file changed, 1 deletion(-) diff --git a/benchmarks/coremark/coremark_sweep.py b/benchmarks/coremark/coremark_sweep.py index f725ad266..162bbd88a 100644 --- a/benchmarks/coremark/coremark_sweep.py +++ b/benchmarks/coremark/coremark_sweep.py @@ -29,7 +29,6 @@ import os -import re # list of architectures to run. arch32_list = [ "rv32gc_zba_zbb_zbc", From fd97108dc33ffab30c1d31fdd1148594cbac8f38 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 23 Mar 2024 17:55:59 -0700 Subject: [PATCH 06/12] Update testbench-fp to support Zfa in FPU modules --- testbench/testbench-fp.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/testbench/testbench-fp.sv b/testbench/testbench-fp.sv index 5eab7c7ec..626e73bb4 100644 --- a/testbench/testbench-fp.sv +++ b/testbench/testbench-fp.sv @@ -719,7 +719,7 @@ module testbenchfp; .XSNaN(XSNaN), .YSNaN(YSNaN), .ZSNaN(ZSNaN), .CvtLzcIn(CvtLzcInE), .IntZero, .FmaASticky(ASticky), .FmaSe(Se), .FmaSm(Sm), .FmaSCnt(SCnt), .FmaAs(As), .FmaPs(Ps), .Fmt(ModFmt), .Frm(FrmVal), - .PostProcFlg(Flg), .PostProcRes(FpRes), .FCvtIntRes(IntRes)); + .PostProcFlg(Flg), .PostProcRes(FpRes), .FCvtIntRes(IntRes), .Zfa(1'b0)); if (TEST === "cvtfp" | TEST === "cvtint" | TEST === "all") begin : fcvt fcvt #(P) fcvt (.Xs(Xs), .Xe(Xe), .Xm(Xm), .Int(SrcA), .ToInt(WriteIntVal), @@ -729,7 +729,7 @@ module testbenchfp; end if (TEST === "cmp" | TEST === "all") begin: fcmp - fcmp #(P) fcmp (.Fmt(ModFmt), .OpCtrl(OpCtrlVal), .Xs, .Ys, .Xe, .Ye, + fcmp #(P) fcmp (.Fmt(ModFmt), .OpCtrl(OpCtrlVal), .Zfa(1'b0), .Xs, .Ys, .Xe, .Ye, .Xm, .Ym, .XZero, .YZero, .CmpIntRes(CmpRes), .XNaN, .YNaN, .XSNaN, .YSNaN, .X, .Y, .CmpNV(CmpFlg[4]), .CmpFpRes(FpCmpRes)); end From b3661a0af488e2cda316afc080bfa5084886a20d Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 24 Mar 2024 12:31:49 -0700 Subject: [PATCH 07/12] Removed unused WALLY-lrsc reference outputs that were incorrect and are not used because Sail is the reference instead --- .../references/WALLY-lrsc-01.reference_output | 8 ------- .../references/WALLY-lrsc-01.reference_output | 24 ------------------- 2 files changed, 32 deletions(-) delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-lrsc-01.reference_output delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-lrsc-01.reference_output diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-lrsc-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-lrsc-01.reference_output deleted file mode 100644 index c40c4a22b..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-lrsc-01.reference_output +++ /dev/null @@ -1,8 +0,0 @@ -fffffffe -00000000 -0000002a -fffffffd -00000001 -0000002a -00000000 -00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-lrsc-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-lrsc-01.reference_output deleted file mode 100644 index 88088c5a9..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-lrsc-01.reference_output +++ /dev/null @@ -1,24 +0,0 @@ -fffffffe -ffffffff -00000000 -00000000 -0000002a -00000000 -fffffffd -ffffffff -00000001 -00000000 -0000002a -00000000 -fffffffb -fffffff7 -00000000 -00000000 -0000002c -00000000 -ffffffef -ffffffdf -00000001 -00000000 -0000002c -00000000 From 2d60b48db4ca877385f676efb712aab5ae901658 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 24 Mar 2024 14:42:09 -0700 Subject: [PATCH 08/12] Added #! so coremark_sweep.py is executable --- Makefile | 2 +- benchmarks/coremark/coremark_sweep.py | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) mode change 100644 => 100755 benchmarks/coremark/coremark_sweep.py diff --git a/Makefile b/Makefile index 877e69e52..f8bd79d5a 100644 --- a/Makefile +++ b/Makefile @@ -6,7 +6,7 @@ all: make install make riscof make testfloat - make verify +# make verify make coverage make benchmarks diff --git a/benchmarks/coremark/coremark_sweep.py b/benchmarks/coremark/coremark_sweep.py old mode 100644 new mode 100755 index 162bbd88a..e1b6c6573 --- a/benchmarks/coremark/coremark_sweep.py +++ b/benchmarks/coremark/coremark_sweep.py @@ -1,3 +1,4 @@ +#!/usr/bin/python ################################################## ## coremark_sweep.py From 5e53aa4de77268f6f70a238cd665e53f6b8f388b Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 24 Mar 2024 15:19:36 -0700 Subject: [PATCH 09/12] Updated tool chain installation instructions and added a script for docker installation --- bin/docker.sh | 25 +++++++++++++++++++++++++ bin/wally-tool-chain-install.sh | 19 +++++++------------ 2 files changed, 32 insertions(+), 12 deletions(-) create mode 100644 bin/docker.sh diff --git a/bin/docker.sh b/bin/docker.sh new file mode 100644 index 000000000..3b827398c --- /dev/null +++ b/bin/docker.sh @@ -0,0 +1,25 @@ +# script to install docker +# based on https://docs.docker.com/engine/install/ubuntu/ +# from Kunlin Han, entered by David Harris + +# Add Docker's official GPG key: +sudo apt-get update +sudo apt-get install ca-certificates curl +sudo install -m 0755 -d /etc/apt/keyrings +sudo curl -fsSL https://download.docker.com/linux/ubuntu/gpg -o /etc/apt/keyrings/docker.asc +sudo chmod a+r /etc/apt/keyrings/docker.asc + +# Add the repository to Apt sources: +echo \ + "deb [arch=$(dpkg --print-architecture) signed-by=/etc/apt/keyrings/docker.asc] https://download.docker.com/linux/ubuntu \ + $(. /etc/os-release && echo "$VERSION_CODENAME") stable" | \ + sudo tee /etc/apt/sources.list.d/docker.list > /dev/null +sudo apt-get update +sudo apt-get install docker-ce docker-ce-cli containerd.io docker-buildx-plugin docker-compose-plugin + +# verify +sudo docker run hello-world + +# install podman +sudo apt-get -y install podman + \ No newline at end of file diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 2dfc751e8..af3789564 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -46,7 +46,7 @@ sudo mkdir -p $RISCV # Update and Upgrade tools (see https://itsfoss.com/apt-update-vs-upgrade/) sudo apt update -y sudo apt upgrade -y -sudo apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev python3-pip pkg-config opam z3 zlib1g-dev automake autotools-dev libmpc-dev libmpfr-dev gperf libtool patchutils bc +sudo apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev python3-pip pkg-config opam z3 zlib1g-dev automake autotools-dev libmpc-dev libmpfr-dev gperf libtool patchutils bc mutt # Other python libraries used through the book. sudo pip3 install sphinx sphinx_rtd_theme matplotlib scipy scikit-learn adjustText lief markdown @@ -60,12 +60,10 @@ fi # gcc cross-compiler (https://github.com/riscv-collab/riscv-gnu-toolchain) # To install GCC from source can take hours to compile. # This configuration enables multilib to target many flavors of RISC-V. -# This book is tested with GCC 12.2 (tagged 2023.01.31), but will likely work with newer versions as well. -# Note that GCC12.2 has binutils 2.39, which has a known performance bug that causes -# objdump to run 100x slower than in previous versions, causing riscof to make versy slowly. -# However GCC12.x is needed for bit manipulation instructions. There is an open issue to fix this: -# https://github.com/riscv-collab/riscv-gnu-toolchain/issues/1188 - +# This book is tested with GCC 13.2.0 +# Versions newer than 2023-12-20 fail to compile the RISC-V arch test with an error: +# cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/jalr-01.S:72: Error: illegal operands `la x0,5b' +# PR *** submitted to fix riscv-arch-test to be compatible with latest GCC by modifying test_macros.h for TEST_JALR_OP cd $RISCV git clone https://github.com/riscv/riscv-gnu-toolchain cd riscv-gnu-toolchain @@ -99,7 +97,7 @@ make install # Spike (https://github.com/riscv-software-src/riscv-isa-sim) # Spike also takes a while to install and compile, but this can be done concurrently -#with the GCC installation. After the build, we need to change two Makefiles to support atomic instructions. +# with the GCC installation. cd $RISCV git clone https://github.com/riscv-software-src/riscv-isa-sim mkdir -p riscv-isa-sim/build @@ -107,10 +105,7 @@ cd riscv-isa-sim/build ../configure --prefix=$RISCV make -j ${NUM_THREADS} make install -cd ../arch_test_target/spike/device -# dh 2/5/24: these should be obsolete -#sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include -#sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include + # Wally needs Verilator 5.021 or later. # Verilator needs to be built from scratch to get the latest version From f0b29d30832037bb81ed0e915261ae946f46aa06 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 24 Mar 2024 17:05:32 -0700 Subject: [PATCH 10/12] AMO max/min comparator optimization --- sim/wave.do | 6 +----- src/lsu/amoalu.sv | 40 ++++++++++++++++++++++++++++------------ 2 files changed, 29 insertions(+), 17 deletions(-) diff --git a/sim/wave.do b/sim/wave.do index 8717f667d..7c8eae184 100644 --- a/sim/wave.do +++ b/sim/wave.do @@ -256,7 +256,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-c add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/SelWay add wave -noupdate -expand -group lsu -expand -group dcache -group {requesting address} /testbench/dut/core/lsu/IEUAdrE add wave -noupdate -expand -group lsu -expand -group dcache -group {requesting address} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLineWay @@ -265,7 +264,7 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/Tag add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ValidWay add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs -color {Blue Violet} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs -color {Blue Violet} /testbench/dut/core/lsu/bus/dcache/dcache/Hit add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/DirtyWay add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitDirtyWay @@ -294,7 +293,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM w add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/LineByteMask -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelData} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearValidWay} @@ -316,7 +314,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM w add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/bwe} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/RAM} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelNonHit} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelData} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ClearValidWay} @@ -426,7 +423,6 @@ add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group typ add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWFaultM add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/DCacheStallM add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM diff --git a/src/lsu/amoalu.sv b/src/lsu/amoalu.sv index 4d6330215..f4b12d4af 100644 --- a/src/lsu/amoalu.sv +++ b/src/lsu/amoalu.sv @@ -37,22 +37,38 @@ module amoalu import cvw::*; #(parameter cvw_t P) ( ); logic [P.XLEN-1:0] a, b, y; + logic sngd, eq, lt, eq32, lt32, w64; + + // Share hardware among the four amomin/amomax comparators + assign sngd = ~LSUFunct7M[5]; // Funct7[5] = 0 for signed amomin/max + assign w64 = (LSUFunct3M[1:0] == 2'b10); // operate on bottom 32 bits + assign sngd32 = sngd & (P.XLEN == 32 | w64); + + comparator #(32) cmp32(a[31:0], b[31:0], sngd32, {eq32, lt32}); + if (P.XLEN == 32) begin + assign lt = lt32; + end else begin + logic equpper, ltupper, lt64; + + comparator #(32) cmpupper(a[63:32], b[63:32], sngd, {equpper, ltupper}); + + assign lt64 = ltupper | equpper & lt32; + assign lt = w64 ? lt32 : lt64; + end - // *** see how synthesis generates this and optimize more structurally if necessary to share hardware - // a single carry chain should be shared for + and the four min/max // and the same mux can be used to select b for swap. always_comb case (LSUFunct7M[6:2]) - 5'b00001: y = b; // amoswap - 5'b00000: y = a + b; // amoadd - 5'b00100: y = a ^ b; // amoxor - 5'b01100: y = a & b; // amoand - 5'b01000: y = a | b; // amoor - 5'b10000: y = ($signed(a) < $signed(b)) ? a : b; // amomin - 5'b10100: y = ($signed(a) >= $signed(b)) ? a : b; // amomax - 5'b11000: y = ($unsigned(a) < $unsigned(b)) ? a : b; // amominu - 5'b11100: y = ($unsigned(a) >= $unsigned(b)) ? a : b; // amomaxu - default: y = 'x; // undefined; *** could change to b for efficiency + 5'b00001: y = b; // amoswap + 5'b00000: y = a + b; // amoadd + 5'b00100: y = a ^ b; // amoxor + 5'b01100: y = a & b; // amoand + 5'b01000: y = a | b; // amoor + 5'b10000: y = lt ? a : b; // amomin + 5'b10100: y = lt ? b : a; // amomax + 5'b11000: y = lt ? a : b; // amominu + 5'b11100: y = lt ? b : a; // amomaxu + default: y = 'x; // undefined; *** could change to b for efficiency endcase // sign extend if necessary From fc158689adb706979c42f8ebff9a7369a717d25b Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 24 Mar 2024 17:15:46 -0700 Subject: [PATCH 11/12] Shared amoalu max/min comparator hardware and removed input sign extend muxes --- src/lsu/amoalu.sv | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/src/lsu/amoalu.sv b/src/lsu/amoalu.sv index f4b12d4af..a6ee53e73 100644 --- a/src/lsu/amoalu.sv +++ b/src/lsu/amoalu.sv @@ -37,12 +37,16 @@ module amoalu import cvw::*; #(parameter cvw_t P) ( ); logic [P.XLEN-1:0] a, b, y; - logic sngd, eq, lt, eq32, lt32, w64; + logic lt, cmp, sngd, sngd32, eq32, lt32, w64; + + // Rename inputs + assign a = ReadDataM; + assign b = IHWriteDataM; // Share hardware among the four amomin/amomax comparators assign sngd = ~LSUFunct7M[5]; // Funct7[5] = 0 for signed amomin/max assign w64 = (LSUFunct3M[1:0] == 2'b10); // operate on bottom 32 bits - assign sngd32 = sngd & (P.XLEN == 32 | w64); + assign sngd32 = sngd & (P.XLEN == 32 | w64); // flip sign in lower 32 bits on 32-bit comparisons only comparator #(32) cmp32(a[31:0], b[31:0], sngd32, {eq32, lt32}); if (P.XLEN == 32) begin @@ -51,12 +55,13 @@ module amoalu import cvw::*; #(parameter cvw_t P) ( logic equpper, ltupper, lt64; comparator #(32) cmpupper(a[63:32], b[63:32], sngd, {equpper, ltupper}); - assign lt64 = ltupper | equpper & lt32; assign lt = w64 ? lt32 : lt64; end - // and the same mux can be used to select b for swap. + assign cmp = lt ^ LSUFunct7M[4]; // flip sense of comparison for maximums + + // AMO ALU always_comb case (LSUFunct7M[6:2]) 5'b00001: y = b; // amoswap @@ -64,27 +69,21 @@ module amoalu import cvw::*; #(parameter cvw_t P) ( 5'b00100: y = a ^ b; // amoxor 5'b01100: y = a & b; // amoand 5'b01000: y = a | b; // amoor - 5'b10000: y = lt ? a : b; // amomin - 5'b10100: y = lt ? b : a; // amomax - 5'b11000: y = lt ? a : b; // amominu - 5'b11100: y = lt ? b : a; // amomaxu + 5'b10000: y = cmp ? a : b; // amomin + 5'b10100: y = cmp ? a : b; // amomax + 5'b11000: y = cmp ? a : b; // amominu + 5'b11100: y = cmp ? a : b; // amomaxu default: y = 'x; // undefined; *** could change to b for efficiency endcase - // sign extend if necessary + // sign extend output if necessary for w64 if (P.XLEN == 32) begin:sext - assign a = ReadDataM; - assign b = IHWriteDataM; assign AMOResultM = y; end else begin:sext // P.XLEN = 64 always_comb - if (LSUFunct3M[1:0] == 2'b10) begin // sign-extend word-length operations - a = {{32{ReadDataM[31]}}, ReadDataM[31:0]}; - b = {{32{IHWriteDataM[31]}}, IHWriteDataM[31:0]}; + if (w64) begin // sign-extend word-length operations AMOResultM = {{32{y[31]}}, y[31:0]}; end else begin - a = ReadDataM; - b = IHWriteDataM; AMOResultM = y; end end From efb68e7eebe04bb4bc1ae79bf028a3da96e1c969 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Tue, 26 Mar 2024 10:28:50 -0700 Subject: [PATCH 12/12] Added dumptvs function to Linux makefile to create linux-testvectors in /opt/riscv directory --- linux/Makefile | 5 +++++ sim/regression-wally | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/linux/Makefile b/linux/Makefile index 46a193090..e2ba5e9f3 100644 --- a/linux/Makefile +++ b/linux/Makefile @@ -40,6 +40,11 @@ install: sudo rm -rf $(RISCV)/$(BUILDROOT) sudo mv $(BUILDROOT) $(RISCV)/$(BUILDROOT) +dumptvs: + export RISCV=$(RISCV) + mkdir -p ../linux-testvectors + cd testvector-generation; ./genInitMem.sh + # Temp rule for debugging test: echo $(shell find $(BUILDROOT)/output/build -maxdepth 2 -type d -regex ".*/linux-[0-9]+\.[0-9]+\.[0-9]+$$") diff --git a/sim/regression-wally b/sim/regression-wally index df4ac86e2..ec420113c 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -61,7 +61,7 @@ else: def getBuildrootTC(boot): INSTR_LIMIT = 1000000 # multiple of 100000; 4M is interesting because it gets into the kernel and enabling VM - MAX_EXPECTED = 246000000 # *** TODO: replace this with a search for the login prompt. + MAX_EXPECTED = 591000000 # *** TODO: replace this with a search for the login prompt. if boot: name="buildrootboot" BRcmd="vsim > {} -c <