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Update ram2 and other memories and associated wrappers

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This commit is contained in:
James Stine 2023-02-01 17:03:48 -06:00
parent 733b877f1d
commit fc5692629a
6 changed files with 234 additions and 100 deletions
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92
pipelined/src/generic/mem/ram2p1r1wbe.sv
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@ -5,7 +5,9 @@
// Two port SRAM 1 read port and 1 write port. // Two port SRAM 1 read port and 1 write port.
// When clk rises Addr and LineWriteData are sampled. // When clk rises Addr and LineWriteData are sampled.
// Following the clk edge read data is output from the sampled Addr. // Following the clk edge read data is output from the sampled Addr.
// Write // Write
// Modified: james.stine@okstate.edu Feb 1, 2023
// Integration of memories
// //
// Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement. // Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement.
// //
@ -42,31 +44,79 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) (
output logic [WIDTH-1:0] rd1 output logic [WIDTH-1:0] rd1
); );
logic [WIDTH-1:0] mem[DEPTH-1:0]; logic [WIDTH-1:0] mem[DEPTH-1:0];
localparam SRAMWIDTH = 32;
localparam SRAMNUMSETS = SRAMWIDTH/WIDTH;
// *************************************************************************** // ***************************************************************************
// TRUE Smem macro // TRUE Smem macro
// *************************************************************************** // ***************************************************************************
// *************************************************************************** if (`USE_SRAM == 1 && WIDTH == 68 && DEPTH == 1024) begin
// READ first SRAM model
// *************************************************************************** ram2p1r1wbe_1024x68 memory1(.CLKA(clk), .CLKB(clk),
integer i; .CEBA(~ce1), .CEBB(~ce2),
.WEBA('0), .WEBB(~we2),
.AA(ra1), .AB(wa2),
.DA('0),
.DB(wd2),
.BWEBA('0), .BWEBB('1),
.QA(rd1),
.QB());
// Read end else if (`USE_SRAM == 1 && WIDTH == 2 && DEPTH == 1024) begin
always_ff @(posedge clk)
if(ce1) rd1 <= #1 mem[ra1];
// Write divided into part for bytes and part for extra msbs
if(WIDTH >= 8)
always @(posedge clk)
if (ce2 & we2)
for(i = 0; i < WIDTH/8; i++)
if(bwe2[i]) mem[wa2][i*8 +: 8] <= #1 wd2[i*8 +: 8];
if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8
always @(posedge clk)
if (ce2 & we2 & bwe2[WIDTH/8])
mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= #1 wd2[WIDTH-1:WIDTH-WIDTH%8];
logic [SRAMWIDTH-1:0] SRAMReadData;
logic [SRAMWIDTH-1:0] SRAMWriteData;
logic [SRAMWIDTH-1:0] RD1Sets[SRAMNUMSETS-1:0];
logic [SRAMNUMSETS-1:0] SRAMBitMaskPre;
logic [SRAMWIDTH-1:0] SRAMBitMask;
logic [$clog2(DEPTH)-1:0] RA1Q;
onehotdecoder #($clog2(SRAMNUMSETS)) oh1(wa2[$clog2(SRAMNUMSETS)-1:0], SRAMBitMaskPre);
genvar index;
for (index = 0; index < SRAMNUMSETS; index++) begin:readdatalinesetsmux
assign RD1Sets[index] = SRAMReadData[(index*WIDTH)+WIDTH-1 : (index*WIDTH)];
assign SRAMWriteData[index*2+1:index*2] = wd2;
assign SRAMBitMask[index*2+1:index*2] = {2{SRAMBitMaskPre[index]}};
end
flopen #($clog2(DEPTH)) mem_reg1 (clk, ce1, ra1, RA1Q);
assign rd1 = RD1Sets[RA1Q[$clog2(SRAMWIDTH)-1:0]];
ram2p1r1wbe_64x32 memory2(.CLKA(clk), .CLKB(clk),
.CEBA(~ce1), .CEBB(~ce2),
.WEBA('0), .WEBB(~we2),
.AA(ra1[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]),
.AB(wa2[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]),
.DA('0),
.DB(SRAMWriteData),
.BWEBA('0), .BWEBB(SRAMBitMask),
.QA(SRAMReadData),
.QB());
end else begin
// ***************************************************************************
// READ first SRAM model
// ***************************************************************************
integer i;
// Read
always_ff @(posedge clk)
if(ce1) rd1 <= #1 mem[ra1];
// Write divided into part for bytes and part for extra msbs
if(WIDTH >= 8)
always @(posedge clk)
if (ce2 & we2)
for(i = 0; i < WIDTH/8; i++)
if(bwe2[i]) mem[wa2][i*8 +: 8] <= #1 wd2[i*8 +: 8];
if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8
always @(posedge clk)
if (ce2 & we2 & bwe2[WIDTH/8])
mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= #1 wd2[WIDTH-1:WIDTH-WIDTH%8];
end
endmodule endmodule

18
pipelined/src/generic/mem/ram2p1r1wbe_1024x69.sv → pipelined/src/generic/mem/ram2p1r1wbe_1024x68.sv
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@ -1,5 +1,5 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// ram2p1rwbe_1024x69.sv // ram2p1rwbe_1024x68.sv
// //
// Written: james.stine@okstate.edu 28 January 2023 // Written: james.stine@okstate.edu 28 January 2023
// Modified: // Modified:
@ -24,7 +24,7 @@
// and limitations under the License. // and limitations under the License.
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
module ram2p1r1wbe_1024x69( module ram2p1r1wbe_1024x68(
input logic CLKA, input logic CLKA,
input logic CLKB, input logic CLKB,
input logic CEBA, input logic CEBA,
@ -33,16 +33,16 @@ module ram2p1r1wbe_1024x69(
input logic WEBB, input logic WEBB,
input logic [9:0] AA, input logic [9:0] AA,
input logic [9:0] AB, input logic [9:0] AB,
input logic [68:0] DA, input logic [67:0] DA,
input logic [68:0] DB, input logic [67:0] DB,
input logic [68:0] BWEBA, input logic [67:0] BWEBA,
input logic [68:0] BWEBB, input logic [67:0] BWEBB,
output logic [68:0] QA, output logic [67:0] QA,
output logic [68:0] QB output logic [67:0] QB
); );
// replace "generic1024x69RAM" with "TSDN..1024X69.." module from your memory vendor // replace "generic1024x69RAM" with "TSDN..1024X69.." module from your memory vendor
generic1024x69RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, generic1024x68RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB,
.AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
endmodule endmodule

48
pipelined/src/generic/mem/ram2p1r1wbe_64x32.sv Executable file
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@ -0,0 +1,48 @@
///////////////////////////////////////////
// ram2p1rwbe_64x32.sv
//
// Written: james.stine@okstate.edu 28 January 2023
// Modified:
//
// Purpose: RAM wrapper for instantiating RAM IP
//
// A component of the CORE-V-WALLY configurable RISC-V project.
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module ram2p1r1wbe_64x32(
input logic CLKA,
input logic CLKB,
input logic CEBA,
input logic CEBB,
input logic WEBA,
input logic WEBB,
input logic [5:0] AA,
input logic [5:0] AB,
input logic [31:0] DA,
input logic [31:0] DB,
input logic [31:0] BWEBA,
input logic [31:0] BWEBB,
output logic [31:0] QA,
output logic [31:0] QB
);
// replace "generic64x32RAM" with "TSDN..64X32.." module from your memory vendor
generic64x32RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB,
.AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
endmodule

137
pipelined/src/generic/mem/rom1p1r.sv
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@ -27,74 +27,73 @@
`include "wally-config.vh" `include "wally-config.vh"
module rom1p1r module rom1p1r #(parameter ADDR_WIDTH = 8,
#( parameter DATA_WIDTH = 32,
//-------------------------------------------------------------------------- parameter PRELOAD_ENABLED = 0)
parameter ADDR_WIDTH = 8, (input logic clk,
// Addr Width in bits : 2 **ADDR_WIDTH = RAM Depth input logic ce,
parameter DATA_WIDTH = 32, // Data Width in bits input logic [ADDR_WIDTH-1:0] addr,
parameter PRELOAD_ENABLED = 0 output logic [DATA_WIDTH-1:0] dout
//---------------------------------------------------------------------- );
) (
input logic clk,
input logic ce,
input logic [ADDR_WIDTH-1:0] addr,
output logic [DATA_WIDTH-1:0] dout
);
// Core Memory
logic [DATA_WIDTH-1:0] ROM [(2**ADDR_WIDTH)-1:0];
always @ (posedge clk) begin // Core Memory
if(ce) dout <= ROM[addr]; logic [DATA_WIDTH-1:0] ROM [(2**ADDR_WIDTH)-1:0];
end if (`USE_SRAM == 1 && DATA_WIDTH == 64 && `XLEN == 64) begin
rom1p1r_128x64 rom1 (.CLK(clk), .CEB(~ce), .A(addr[6:0]), .Q(dout));
// for FPGA, initialize with zero-stage bootloader end else begin
if(PRELOAD_ENABLED) begin always @ (posedge clk) begin
initial begin if(ce) dout <= ROM[addr];
ROM[0] = 64'h9581819300002197; end
ROM[1] = 64'h4281420141014081;
ROM[2] = 64'h4481440143814301; // for FPGA, initialize with zero-stage bootloader
ROM[3] = 64'h4681460145814501; if(PRELOAD_ENABLED) begin
ROM[4] = 64'h4881480147814701; initial begin
ROM[5] = 64'h4a814a0149814901; ROM[0] = 64'h9581819300002197;
ROM[6] = 64'h4c814c014b814b01; ROM[1] = 64'h4281420141014081;
ROM[7] = 64'h4e814e014d814d01; ROM[2] = 64'h4481440143814301;
ROM[8] = 64'h0110011b4f814f01; ROM[3] = 64'h4681460145814501;
ROM[9] = 64'h059b45011161016e; ROM[4] = 64'h4881480147814701;
ROM[10] = 64'h0004063705fe0010; ROM[5] = 64'h4a814a0149814901;
ROM[11] = 64'h05a000ef8006061b; ROM[6] = 64'h4c814c014b814b01;
ROM[12] = 64'h0ff003930000100f; ROM[7] = 64'h4e814e014d814d01;
ROM[13] = 64'h4e952e3110060e37; ROM[8] = 64'h0110011b4f814f01;
ROM[14] = 64'hc602829b0053f2b7; ROM[9] = 64'h059b45011161016e;
ROM[15] = 64'h2023fe02dfe312fd; ROM[10] = 64'h0004063705fe0010;
ROM[16] = 64'h829b0053f2b7007e; ROM[11] = 64'h05a000ef8006061b;
ROM[17] = 64'hfe02dfe312fdc602; ROM[12] = 64'h0ff003930000100f;
ROM[18] = 64'h4de31efd000e2023; ROM[13] = 64'h4e952e3110060e37;
ROM[19] = 64'h059bf1402573fdd0; ROM[14] = 64'hc602829b0053f2b7;
ROM[20] = 64'h0000061705e20870; ROM[15] = 64'h2023fe02dfe312fd;
ROM[21] = 64'h0010029b01260613; ROM[16] = 64'h829b0053f2b7007e;
ROM[22] = 64'h11010002806702fe; ROM[17] = 64'hfe02dfe312fdc602;
ROM[23] = 64'h84b2842ae426e822; ROM[18] = 64'h4de31efd000e2023;
ROM[24] = 64'h892ee04aec064511; ROM[19] = 64'h059bf1402573fdd0;
ROM[25] = 64'h06e000ef07e000ef; ROM[20] = 64'h0000061705e20870;
ROM[26] = 64'h979334fd02905563; ROM[21] = 64'h0010029b01260613;
ROM[27] = 64'h07930177d4930204; ROM[22] = 64'h11010002806702fe;
ROM[28] = 64'h4089093394be2004; ROM[23] = 64'h84b2842ae426e822;
ROM[29] = 64'h04138522008905b3; ROM[24] = 64'h892ee04aec064511;
ROM[30] = 64'h19e3014000ef2004; ROM[25] = 64'h06e000ef07e000ef;
ROM[31] = 64'h64a2644260e2fe94; ROM[26] = 64'h979334fd02905563;
ROM[32] = 64'h6749808261056902; ROM[27] = 64'h07930177d4930204;
ROM[33] = 64'hdfed8b8510472783; ROM[28] = 64'h4089093394be2004;
ROM[34] = 64'h2423479110a73823; ROM[29] = 64'h04138522008905b3;
ROM[35] = 64'h10472783674910f7; ROM[30] = 64'h19e3014000ef2004;
ROM[36] = 64'h20058693ffed8b89; ROM[31] = 64'h64a2644260e2fe94;
ROM[37] = 64'h05a1118737836749; ROM[32] = 64'h6749808261056902;
ROM[38] = 64'hfed59be3fef5bc23; ROM[33] = 64'hdfed8b8510472783;
ROM[39] = 64'h1047278367498082; ROM[34] = 64'h2423479110a73823;
ROM[40] = 64'h47858082dfed8b85; ROM[35] = 64'h10472783674910f7;
ROM[41] = 64'h40a7853b4015551b; ROM[36] = 64'h20058693ffed8b89;
ROM[42] = 64'h808210a7a02367c9; ROM[37] = 64'h05a1118737836749;
end ROM[38] = 64'hfed59be3fef5bc23;
end ROM[39] = 64'h1047278367498082;
ROM[40] = 64'h47858082dfed8b85;
endmodule // bytewrite_tdp_ram_rf ROM[41] = 64'h40a7853b4015551b;
ROM[42] = 64'h808210a7a02367c9;
end
end
end
endmodule

2
pipelined/src/generic/mem/rom1p1r_128x32.sv
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@ -4,7 +4,7 @@
// Written: james.stine@okstate.edu 28 January 2023 // Written: james.stine@okstate.edu 28 January 2023
// Modified: // Modified:
// //
// Purpose: RAM wrapper for instantiating RAM IP // Purpose: ROM wrapper for instantiating ROM IP
// //
// A component of the CORE-V-WALLY configurable RISC-V project. // A component of the CORE-V-WALLY configurable RISC-V project.
// //

37
pipelined/src/generic/mem/rom1p1r_128x64.sv Executable file
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@ -0,0 +1,37 @@
///////////////////////////////////////////
// rom1p1r_128x64.sv
//
// Written: james.stine@okstate.edu 28 January 2023
// Modified:
//
// Purpose: ROM wrapper for instantiating ROM IP
//
// A component of the CORE-V-WALLY configurable RISC-V project.
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module rom1p1r_128x64(
input logic CLK,
input logic CEB,
input logic [6:0] A,
output logic [63:0] Q
);
// replace "generic64x128RAM" with "TS3N..64X128.." module from your memory vendor
generic64x128ROM romIP (.CLK, .CEB, .A, .Q);
endmodule