From fc45fb866930dc9436d55bae2cad072781967e0f Mon Sep 17 00:00:00 2001 From: James Stine Date: Mon, 3 Jun 2024 17:27:40 -0500 Subject: [PATCH] fix csr.sv --- src/privileged/csr.sv | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index fac432251..9641fa2d4 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -92,7 +92,12 @@ module csr import cvw::*; #(parameter cvw_t P) ( // output logic [P.XLEN-1:0] CSRReadValW, // value read from CSR output logic IllegalCSRAccessM, // Illegal CSR access: CSR doesn't exist or is inaccessible at this privilege level - output logic BigEndianM // memory access is big-endian based on privilege mode and STATUS register endian fields + output logic BigEndianM, // memory access is big-endian based on privilege mode and STATUS register endian fields + // Debug scan chain + input logic DebugCapture, + input logic DebugScanEn, + input logic DebugScanIn, + output logic DebugScanOut ); localparam MIP = 12'h344; @@ -236,7 +241,7 @@ module csr import cvw::*; #(parameter cvw_t P) ( .MEDELEG_REGW, .MIDELEG_REGW,.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, .MIP_REGW, .MIE_REGW, .WriteMSTATUSM, .WriteMSTATUSHM, .IllegalCSRMAccessM, .IllegalCSRMWriteReadonlyM, - .MENVCFG_REGW); + .MENVCFG_REGW, .DebugCapture, .DebugScanEn, .DebugScanIn, .DebugScanOut); if (P.S_SUPPORTED) begin:csrs