diff --git a/pipelined/src/uncore/ram3.sv b/pipelined/src/uncore/ram3.sv index ad568b70c..90a3196ba 100644 --- a/pipelined/src/uncore/ram3.sv +++ b/pipelined/src/uncore/ram3.sv @@ -56,7 +56,7 @@ module ram #(parameter BASE=0, RANGE = 65535) ( logic memwrite; logic [3:0] busycount; - swbytemask swbytemask(.HSIZED, .HADDRD(A[2:0]), .ByteMask(ByteMaskM)); + swbytemask swbytemask(.HSIZED, .HADDRD(HWADDR[2:0]), .ByteMask(ByteMaskM)); assign initTrans = HREADY & HSELRam & (HTRANS != 2'b00); @@ -83,6 +83,7 @@ module ram #(parameter BASE=0, RANGE = 65535) ( assign HRESPRam = 0; // OK localparam ADDR_WDITH = $clog2(RANGE/8); + localparam OFFSET = $clog2(`XLEN/8); // Rising HREADY edge detector // Indicates when ram is finishing up @@ -96,9 +97,9 @@ module ram #(parameter BASE=0, RANGE = 65535) ( bram2p1r1w #(`XLEN/8, 8, ADDR_WDITH) memory(.clk(HCLK), .enaA(1'b1), - .addrA(A[ADDR_WDITH+2:3]), .doutA(HREADRam), + .addrA(A[ADDR_WDITH+OFFSET-1:OFFSET]), .doutA(HREADRam), .enaB(memwrite & risingHREADYRam), .weB(ByteMaskM), - .addrB(HWADDR[ADDR_WDITH+2:3]), .dinB(HWDATA)); + .addrB(HWADDR[ADDR_WDITH+OFFSET-1:OFFSET]), .dinB(HWDATA)); endmodule diff --git a/pipelined/testbench/testbench-linux.sv b/pipelined/testbench/testbench-linux.sv index 6044d124d..dfaa70e61 100644 --- a/pipelined/testbench/testbench-linux.sv +++ b/pipelined/testbench/testbench-linux.sv @@ -353,21 +353,21 @@ module testbench; ProgramLabelMapFile = {linuxImageDir,"disassembly/vmlinux.objdump.lab"}; // initialize bootrom memFile = $fopen({testvectorDir,"bootmem.bin"}, "rb"); - readResult = $fread(dut.uncore.bootrom.bootrom.RAM,memFile); + readResult = $fread(dut.uncore.bootrom.bootrom.memory.RAM,memFile); $fclose(memFile); // initialize RAM if (CHECKPOINT==0) memFile = $fopen({testvectorDir,"ram.bin"}, "rb"); else memFile = $fopen({checkpointDir,"ram.bin"}, "rb"); - readResult = $fread(dut.uncore.ram.ram.RAM,memFile); + readResult = $fread(dut.uncore.ram.ram.memory.RAM,memFile); $fclose(memFile); if (CHECKPOINT==0) begin // normal traceFileM = $fopen({testvectorDir,"all.txt"}, "r"); traceFileE = $fopen({testvectorDir,"all.txt"}, "r"); InstrCountW = '0; end else begin // checkpoint - //$readmemh({checkpointDir,"ram.txt"}, dut.uncore.ram.ram.RAM); + //$readmemh({checkpointDir,"ram.txt"}, dut.uncore.ram.ram.memory.RAM); traceFileE = $fopen({checkpointDir,"all.txt"}, "r"); traceFileM = $fopen({checkpointDir,"all.txt"}, "r"); InstrCountW = CHECKPOINT; @@ -771,9 +771,9 @@ module testbench; BaseAdr = SATP[43:0] << 12; for (i = 2; i >= 0; i--) begin PAdr = BaseAdr + (VPN[i] << 3); - // ram.RAM is 64-bit addressed. PAdr specifies a byte. We right shift + // ram.memory.RAM is 64-bit addressed. PAdr specifies a byte. We right shift // by 3 (the PTE size) to get the requested 64-bit PTE. - PTE = dut.uncore.ram.ram.RAM[PAdr >> 3]; + PTE = dut.uncore.ram.ram.memory.RAM[PAdr >> 3]; PTE_R = PTE[1]; PTE_X = PTE[3]; if (PTE_R | PTE_X) begin diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 9bb2ed029..105493399 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -44,7 +44,7 @@ module testbench; int test, i, errors, totalerrors; logic [31:0] sig32[0:SIGNATURESIZE]; logic [`XLEN-1:0] signature[0:SIGNATURESIZE]; - logic [`XLEN-1:0] testadr; + logic [`XLEN-1:0] testadr, testadrNoBase; string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; logic [31:0] InstrW; @@ -170,6 +170,7 @@ logic [3:0] dummy; test = 1; totalerrors = 0; testadr = 0; + testadrNoBase = 0; // fill memory with defined values to reduce Xs in simulation // Quick note the memory will need to be initialized. The C library does not // guarantee the initialized reads. For example a strcmp can read 6 byte @@ -186,9 +187,9 @@ logic [3:0] dummy; pathname = tvpaths[0]; else pathname = tvpaths[1]; */ memfilename = {pathname, tests[test], ".elf.memfile"}; - if (`IMEM == `MEM_TIM) $readmemh(memfilename, dut.core.ifu.irom.irom.ram.memory.RAM); + if (`IMEM == `MEM_TIM) $readmemh(memfilename, dut.core.ifu.irom.irom.ram.RAM); else $readmemh(memfilename, dut.uncore.ram.ram.memory.RAM); - if (`DMEM == `MEM_TIM) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.memory.RAM); + if (`DMEM == `MEM_TIM) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM); ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"}; ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"}; @@ -243,12 +244,13 @@ logic [3:0] dummy; errors = (i == SIGNATURESIZE+1); // error if file is empty i = 0; testadr = (`RAM_BASE+tests[test+1].atohex())/(`XLEN/8); + testadrNoBase = (tests[test+1].atohex())/(`XLEN/8); /* verilator lint_off INFINITELOOP */ while (signature[i] !== 'bx) begin logic [`XLEN-1:0] sig; - if (`DMEM == `MEM_TIM) sig = dut.core.lsu.dtim.dtim.ram.memory.RAM[testadr+i]; - else sig = dut.uncore.ram.ram.memory.RAM[testadr+i]; -// $display("signature[%h] = %h sig = %h", i, signature[i], sig); + if (`DMEM == `MEM_TIM) sig = dut.core.lsu.dtim.dtim.ram.RAM[testadr+i]; + else sig = dut.uncore.ram.ram.memory.RAM[testadrNoBase+i]; + //$display("signature[%h] = %h sig = %h", i, signature[i], sig); if (signature[i] !== sig & //if (signature[i] !== dut.core.lsu.dtim.ram.memory.RAM[testadr+i] & (signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin // ***i+1? @@ -284,9 +286,9 @@ logic [3:0] dummy; //pathname = tvpaths[tests[0]]; memfilename = {pathname, tests[test], ".elf.memfile"}; //$readmemh(memfilename, dut.uncore.ram.ram.memory.RAM); - if (`IMEM == `MEM_TIM) $readmemh(memfilename, dut.core.ifu.irom.irom.ram.memory.RAM); + if (`IMEM == `MEM_TIM) $readmemh(memfilename, dut.core.ifu.irom.irom.ram.RAM); else $readmemh(memfilename, dut.uncore.ram.ram.memory.RAM); - if (`DMEM == `MEM_TIM) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.memory.RAM); + if (`DMEM == `MEM_TIM) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM); ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"}; ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};