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Working on reading instruction from TIM

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David Harris 2021-01-30 01:57:51 -05:00
parent 61fd7c4499
commit fc1fb94217
2 changed files with 3 additions and 0 deletions
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1
wally-pipelined/src/ahblite.sv
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@ -44,6 +44,7 @@ module ahblite (
input logic DReadM, DWriteM, input logic DReadM, DWriteM,
input logic [`XLEN-1:0] DWDataM, input logic [`XLEN-1:0] DWDataM,
input logic [1:0] DSizeM, input logic [1:0] DSizeM,
// Return from bus
output logic [`XLEN-1:0] DRData, output logic [`XLEN-1:0] DRData,
// output logic DReady, // output logic DReady,
// AHB-Lite external signals // AHB-Lite external signals

2
wally-pipelined/src/wallypipelinedhart.sv
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@ -55,6 +55,7 @@ module wallypipelinedhart (
// new signals that must connect through DP // new signals that must connect through DP
logic CSRWriteM, PrivilegedM; logic CSRWriteM, PrivilegedM;
logic [`XLEN-1:0] SrcAM; logic [`XLEN-1:0] SrcAM;
// logic [31:0] InstrF;
logic [31:0] InstrD, InstrM; logic [31:0] InstrD, InstrM;
logic [`XLEN-1:0] PCE, PCM, PCLinkW; logic [`XLEN-1:0] PCE, PCM, PCLinkW;
logic [`XLEN-1:0] PCTargetE; logic [`XLEN-1:0] PCTargetE;
@ -100,6 +101,7 @@ module wallypipelinedhart (
.DSizeM(Funct3M[1:0]), .DRData(ReadDataM), //.DReady(), .DSizeM(Funct3M[1:0]), .DRData(ReadDataM), //.DReady(),
.UnsignedLoadM(Funct3M[2]), .UnsignedLoadM(Funct3M[2]),
.*); .*);
//assign InstrF = ReadDataM[31:0];
// assign UnsignedLoadM = Funct3M[2]; // *** maybe move read extension to dcu // assign UnsignedLoadM = Funct3M[2]; // *** maybe move read extension to dcu
/* /*