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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

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This commit is contained in:
Daniel Torres 2022-07-22 13:52:19 -07:00
commit fbe3a1af12
16 changed files with 1989 additions and 32 deletions
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2
addins/riscv-arch-test

@ -1 +1 @@
Subproject commit e5020bf7b345f8efb96c6c939de3162525b7f545 Subproject commit be67c99bd461742aa1c100bcc0732657faae2230

2
pipelined/src/uncore/uartPC16550D.sv
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@ -206,6 +206,8 @@ module uartPC16550D(
// Modem Status Register (8.6.8) // Modem Status Register (8.6.8)
if (~MEMWb & (A == 3'b110)) if (~MEMWb & (A == 3'b110))
MSR <= #1 Din[3:0]; MSR <= #1 Din[3:0];
else if (~MEMRb & (A == 3'b110))
MSR <= #1 4'b0; // Reading MSR clears the flags in MSR bits 3:0
else begin else begin
MSR[0] <= #1 MSR[0] | CTSb2 ^ CTSbsync; // Delta Clear to Send MSR[0] <= #1 MSR[0] | CTSb2 ^ CTSbsync; // Delta Clear to Send
MSR[1] <= #1 MSR[1] | DSRb2 ^ DSRbsync; // Delta Data Set Ready MSR[1] <= #1 MSR[1] | DSRb2 ^ DSRbsync; // Delta Data Set Ready

BIN
pipelined/srt/sqrttestgen
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33
pipelined/srt/sqrttestgen.c
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@ -1,6 +1,6 @@
/* sqrttestgen.c */ /* sqrttestgen.c */
/* Written 19 October 2021 David_Harris@hmc.edu /* Written 7/22/2022 by Cedar Turek
This program creates test vectors for mantissa component This program creates test vectors for mantissa component
of an IEEE floating point square root. of an IEEE floating point square root.
@ -15,6 +15,7 @@
/* Constants */ /* Constants */
#define ENTRIES 17 #define ENTRIES 17
#define BIGENT 1000
#define RANDOM_VECS 500 #define RANDOM_VECS 500
/* Prototypes */ /* Prototypes */
@ -34,6 +35,9 @@ void main(void)
1.75, 1.875, 1.99999, 1.75, 1.875, 1.99999,
1.1, 1.5, 1.01, 1.001, 1.0001, 1.1, 1.5, 1.01, 1.001, 1.0001,
2/1.1, 2/1.5, 2/1.25, 2/1.125}; 2/1.1, 2/1.5, 2/1.25, 2/1.125};
double bigtest[BIGENT];
double exps[ENTRIES] = {0, 0, 2, 3, 4, 5, 6, 7, 8, 1, 10, double exps[ENTRIES] = {0, 0, 2, 3, 4, 5, 6, 7, 8, 1, 10,
11, 12, 13, 14, 15, 16}; 11, 12, 13, 14, 15, 16};
int i; int i;
@ -44,13 +48,14 @@ void main(void)
exit(1); exit(1);
} }
for (i=0; i<ENTRIES; i++) { // Small Test
aFrac = mans[i]; // for (i=0; i<ENTRIES; i++) {
aExp = exps[i] + bias; // aFrac = mans[i];
rFrac = sqrt(aFrac * pow(2, exps[i])); // aExp = exps[i] + bias;
rExp = (int) (log(rFrac)/log(2) + bias); // rFrac = sqrt(aFrac * pow(2, exps[i]));
output(fptr, aExp, aFrac, rExp, rFrac); // rExp = (int) (log(rFrac)/log(2) + bias);
} // output(fptr, aExp, aFrac, rExp, rFrac);
// }
// WS // WS
// Test 1: sqrt(1) = 1 0000 0000 0000 00 // Test 1: sqrt(1) = 1 0000 0000 0000 00
@ -67,6 +72,16 @@ void main(void)
// output(fptr, a, r); // output(fptr, a, r);
// } // }
// Big Test
for (i=0; i<BIGENT; i++) {
bigtest[i] = random_input();
aFrac = bigtest[i];
aExp = (i - BIGENT/2) + bias;
rFrac = sqrt(aFrac * pow(2, (i - BIGENT/2)));
rExp = (int) (log(rFrac)/log(2) + bias);
output(fptr, aExp, aFrac, rExp, rFrac);
}
fclose(fptr); fclose(fptr);
} }
@ -105,6 +120,6 @@ void printhex(FILE *fptr, double m)
double random_input(void) double random_input(void)
{ {
return 1.0 + rand()/32767.0; return 1.0 + ((rand() % 32768)/32767.0);
} }

1
pipelined/srt/srt-waves.do
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@ -3,4 +3,5 @@ add wave -noupdate /testbench/srt/*
add wave -noupdate /testbench/srt/sotfc2/* add wave -noupdate /testbench/srt/sotfc2/*
add wave -noupdate /testbench/srt/preproc/* add wave -noupdate /testbench/srt/preproc/*
add wave -noupdate /testbench/srt/postproc/* add wave -noupdate /testbench/srt/postproc/*
add wave -noupdate /testbench/srt/expcalc/*
add wave -noupdate /testbench/srt/divcounter/* add wave -noupdate /testbench/srt/divcounter/*

22
pipelined/srt/srt.sv
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@ -389,11 +389,11 @@ module expcalc(
input logic Sqrt, input logic Sqrt,
output logic [`NE-1:0] calcExp output logic [`NE-1:0] calcExp
); );
logic [`NE-1:0] SExp, DExp, SXExp; logic [`NE+1:0] SExp, DExp, SXExp;
assign SXExp = XExp - (`NE)'(`BIAS); assign SXExp = {2'b00, XExp} - (`NE+2)'(`BIAS);
assign SExp = {1'b0, SXExp[`NE-1:1]} + (`NE)'(`BIAS); assign SExp = (SXExp >> 1) + (`NE+2)'(`BIAS);
assign DExp = XExp - YExp + (`NE)'(`BIAS); assign DExp = {2'b00, XExp} - {2'b00, YExp} + (`NE+2)'(`BIAS);
assign calcExp = Sqrt ? SExp : DExp; assign calcExp = Sqrt ? SExp[`NE-1:0] : DExp[`NE-1:0];
endmodule endmodule
@ -462,11 +462,13 @@ module srtpostproc(
end end
assign floatRes = S[`DIVLEN] ? S[`DIVLEN:1] : S[`DIVLEN-1:0]; assign floatRes = S[`DIVLEN] ? S[`DIVLEN:1] : S[`DIVLEN-1:0];
assign intRes = intS[`DIVLEN] ? intS[`DIVLEN:1] : intS[`DIVLEN-1:0]; assign intRes = intS[`DIVLEN] ? intS[`DIVLEN:1] : intS[`DIVLEN-1:0];
assign shiftRem = (intRem >>> (`DIVLEN - dur + 2)); assign shiftRem = (intRem >> (zeroCntD));
always_comb always_comb begin
if (Int) Result = intRes >> (`DIVLEN - dur); if (Int) begin
else if (Mod) Result = shiftRem[`DIVLEN-1:0]; if (Mod) Result = shiftRem[`DIVLEN-1:0];
else Result = floatRes; else Result = intRes >> (`DIVLEN - dur);
end else Result = floatRes;
end
assign calcSign = XSign ^ YSign; assign calcSign = XSign ^ YSign;
endmodule endmodule

8
pipelined/srt/testbench.sv
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@ -53,7 +53,7 @@ module testbench;
// Test parameters // Test parameters
parameter MEM_SIZE = 40000; parameter MEM_SIZE = 40000;
parameter MEM_WIDTH = 64+64+64+64; parameter MEM_WIDTH = 64+64+64;
// Test sizes // Test sizes
`define memr 63:0 `define memr 63:0
@ -70,9 +70,9 @@ module testbench;
integer testnum, errors; integer testnum, errors;
// Equip Int, Sqrt, or IntMod test // Equip Int, Sqrt, or IntMod test
assign Int = 1'b1; assign Int = 1'b0;
assign Mod = 1'b0; assign Mod = 1'b0;
assign Sqrt = 1'b0; assign Sqrt = 1'b1;
// Divider // Divider
srt srt(.clk, .Start(req), srt srt(.clk, .Start(req),
@ -101,7 +101,7 @@ module testbench;
begin begin
testnum = 0; testnum = 0;
errors = 0; errors = 0;
$readmemh ("inttestvectors", Tests); $readmemh ("sqrttestvectors", Tests);
Vec = Tests[testnum]; Vec = Tests[testnum];
a = Vec[`mema]; a = Vec[`mema];
{asign, aExp, afrac} = a; {asign, aExp, afrac} = a;

4
pipelined/testbench/tests.vh
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@ -1603,8 +1603,8 @@ string wally32i[] = '{
string wally32periph[] = '{ string wally32periph[] = '{
`WALLYTEST, `WALLYTEST,
"rv32i_m/privilege/WALLY-gpio-01", "rv32i_m/privilege/WALLY-gpio-01",
"rv32i_m/privilege/WALLY-clint-01" "rv32i_m/privilege/WALLY-clint-01",
// "rv32i_m/privilege/WALLY-plic-01" "rv32i_m/privilege/WALLY-plic-01"
// "rv32i_m/privilege/WALLY-uart-01" // "rv32i_m/privilege/WALLY-uart-01"
}; };

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag
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@ -55,6 +55,8 @@ target_tests_nosim = \
WALLY-status-tw-01 \ WALLY-status-tw-01 \
WALLY-gpio-01 \ WALLY-gpio-01 \
WALLY-clint-01 \ WALLY-clint-01 \
WALLY-plic-01 \
WALLY-uart-01 \
rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests)) rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests))

249
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-plic-01.reference_output Normal file
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@ -0,0 +1,249 @@
00000000 # read empty MIP (1.0.0)
00000008 # check GPIO interrupt pending on intPending0
00000000 # Claim gives no interrupt due to zero priority
00000008 # interrupt still pending due to no claim
00000000 # check no interrupts pending
00000800 # MEIP set due to PLIC priority (1.0.1)
00000008 # check GPIO interrupt pending on intPending0
00000003 # claim gives 3 for ID of GPIO
00000000 # check no interrupts pending
00000000 # check no interrupts pending
00000000 # read empty MIP (1.0.2)
00000000 # check GPIO interrupt pending on intPending0
00000000 # claim gives no interrupt due to no intPending
00000000 # no interrupts pending after clear
00000000 # still no interrupts after clear
00000000 # read empty MIP (1.1.0)
00000008 # check GPIO interrupt pending on intPending0
00000003 # Claim gives 3 for ID of GPIO
00000000 # interrupt still pending due to no claim
00000000 # check no interrupts pending
00000800 # MEIP set due to PLIC priority (1.1.1)
00000008 # check GPIO interrupt pending on intPending0
00000003 # claim gives 3 for ID of GPIO
00000000 # check no interrupts pending after claim
00000000 # check no interrupts pending
00000000 # read empty MIP (1.2.0)
00000008 # check GPIO interrupt pending on intPending0
00000003 # Claim gives 3 for ID of GPIO
00000000 # check no interrupts pending after claim
00000000 # check no interrupts pending
00000800 # MEIP set due to PLIC priority (1.2.1)
00000008 # check GPIO interrupt pending on intPending0
00000003 # claim gives 3 for ID of GPIO
00000000 # check no interrupts pending after claim
00000000 # check no interrupts pending
00000000 # read empty MIP (1.3.0)
00000008 # check GPIO interrupt pending on intPending0
00000003 # Claim gives 3 for ID of GPIO
00000000 # check no interrupts pending after claim
00000000 # check no interrupts pending
00000800 # MEIP set due to PLIC priority (1.3.1)
00000008 # check GPIO interrupt pending on intPending0
00000003 # claim gives 3 for ID of GPIO
00000000 # check no interrupts pending after claim
00000000 # check no interrupts pending
00000000 # read empty MIP (1.4.0)
00000008 # check GPIO interrupt pending on intPending0
00000003 # Claim gives 3 for ID of GPIO
00000000 # check no interrupts pending after claim
00000000 # check no interrupts pending
00000800 # MEIP set due to PLIC priority (1.4.1)
00000008 # check GPIO interrupt pending on intPending0
00000003 # claim gives 3 for ID of GPIO
00000000 # check no interrupts pending after claim
00000000 # check no interrupts pending
00000000 # read empty MIP (1.5.0)
00000008 # check GPIO interrupt pending on intPending0
00000003 # Claim gives 3 for ID of GPIO
00000000 # check no interrupts pending after claim
00000000 # check no interrupts pending
00000800 # MEIP set due to PLIC priority (1.5.1)
00000008 # check GPIO interrupt pending on intPending0
00000003 # claim gives 3 for ID of GPIO
00000000 # check no interrupts pending after claim
00000000 # check no interrupts pending
00000000 # read empty MIP (1.6.0)
00000008 # check GPIO interrupt pending on intPending0
00000003 # Claim gives 3 for ID of GPIO
00000000 # check no interrupts pending after claim
00000000 # check no interrupts pending
00000800 # MEIP set due to PLIC priority (1.6.1)
00000008 # check GPIO interrupt pending on intPending0
00000003 # claim gives 3 for ID of GPIO
00000000 # check no interrupts pending after claim
00000000 # check no interrupts pending
00000000 # read empty MIP (1.7.0)
00000008 # check GPIO interrupt pending on intPending0
00000003 # Claim gives 3 for ID of GPIO
00000000 # check no interrupts pending after claim
00000000 # check no interrupts pending
00000800 # MEIP set (2.0)
00000408 # gpio and uart pending
00000003 # claim gpio
00000400 # gpio no longer pending
00000000 # no interrupts pending
00000800 # MEIP set (2.1)
00000408 # gpio and uart pending
00000003 # claim gpio
00000400 # gpio no longer pending
00000000 # no interrupts pending
00000800 # MEIP set (2.2)
00000408 # gpio and uart pending
0000000A # claim uart
00000008 # uart no longer pending
00000000 # no interrupts pending
00000800 # MEIP set (2.3)
00000408 # gpio and uart pending
0000000A # claim uart
00000008 # uart no longer pending
00000000 # no interrupts pending
00000000 # MEIP empty (2.4)
00000408 # gpio and uart pending
0000000A # claim none
00000008 # gpio and uart still pending
00000000 # no interrupts pending
00000A00 # MEIP and SEIP set (3.0)
00000408 # check GPIO and UART interrupt pending on intPending0
00000003 # claim gives 3 for ID of GPIO
00000400 # check GPIO interrupt pending cleared after claim
00000000 # check no interrupts pending
00000200 # SEIP set (3.1)
00000408 # check GPIO and UART interrupt pending on intPending0
00000003 # claim gives 3 for ID of GPIO
00000400 # check GPIO interrupt pending cleared after claim
00000000 # check no interrupts pending
00000200 # SEIP set (3.2)
00000408 # check GPIO and UART interrupt pending on intPending0
0000000A # claim UART
00000008 # GPIO interrupt pending after UART claimcomp
00000000 # check no interrupts pending
00000000 # read empty MIP (3.3)
00000408 # check GPIO and UART interrupt pending on intPending0
0000000A # claim UART
00000008 # check UART interrupt pending cleared after claim
00000000 # check no interrupts pending
00000A00 # MEIP and SEIP set (4.0)
00000400 # UART interrupt pending
0000000A # claim UART
00000000 # check no interrupts pending
00000000 # check no interrupts pending
00000200 # SEIP set (4.1)
00000400 # UART interrupt pending
00000000 # nothing in claim register
00000400 # UART interrupt pending
00000000 # check no interrupts pending
00000A00 # MEIP and SEIP set (4.2)
00000400 # UART interrupt pending
0000000A # claim UART
00000000 # check no interrupts pending
00000000 # check no interrupts pending
00000800 # MEIP set (4.3)
00000400 # UART interrupt pending
0000000A # claim UART
00000000 # check no interrupts pending
00000000 # check no interrupts pending
00000800 # MEIP set (4.4)
00000400 # UART interrupt pending
0000000A # claim UART
00000000 # check no interrupts pending
00000000 # check no interrupts pending
00000200 # SEIP set (4.5)
00000400 # UART interrupt pending
00000000 # nothing in claim register
00000400 # UART interrupt pending
00000000 # check no interrupts pending
00000000 # All disabled (4.6)
00000400 # UART interrupt pending
00000000 # nothing in claim register
00000400 # UART interrupt pending
00000000 # check no interrupts pending
00000200 # SEIP set (5.0)
00000008 # GPIO interrupt pending
00000000 # nothing in claim register
00000008 # GPIO interrupt pending
00000000 # check no interrupts pending
00000A00 # MEIP and SEIP set (5.1)
00000008 # GPIO interrupt pending
00000003 # claim gives 3 for ID of GPIO
00000000 # check no interrupts pending
00000000 # check no interrupts pending
00000800 # MEIP set (5.2)
00000008 # GPIO interrupt pending
00000003 # claim gives 3 for ID of GPIO
00000000 # check no interrupts pending
00000000 # check no interrupts pending
00000A00 # MEIP and SEIP set (5.3)
00000008 # GPIO interrupt pending
00000003 # claim gives 3 for ID of GPIO
00000000 # check no interrupts pending
00000000 # check no interrupts pending
00000800 # MEIP set (5.4)
00000008 # GPIO interrupt pending
00000003 # claim gives 3 for ID of GPIO
00000000 # check no interrupts pending
00000000 # check no interrupts pending
00000200 # SEIP set (5.5)
00000008 # GPIO interrupt pending
00000000 # nothing in claim register
00000008 # GPIO interrupt pending
00000000 # check no interrupts pending
00000000 # read empty MIP (5.6)
00000008 # GPIO interrupt pending
00000000 # nothing in claim register
00000008 # GPIO interrupt pending
00000000 # check no interrupts pending
0000000b # written due to goto_s_mode
00000200 # read sip (7.0)
00000408 # check GPIO and UART interrupt pending on intPending0
00000003 # claim gives 3 for ID of GPIO
00000400 # check GPIO interrupt pending cleared after claim
00000000 # check no interrupts pending
00000200 # read sip (7.1)
00000408 # check GPIO and UART interrupt pending on intPending0
00000003 # claim gives 3 for ID of GPIO
00000400 # check GPIO interrupt pending cleared after claim
00000000 # check no interrupts pending
00000200 # read sip (7.2)
00000408 # check GPIO and UART interrupt pending on intPending0
0000000A # claim UART
00000008 # GPIO interrupt pending after UART claimcomp
00000000 # check no interrupts pending
00000200 # read sip (7.3)
00000408 # check GPIO and UART interrupt pending on intPending0
00000003 # claim gives 3 for ID of GPIO
00000400 # check GPIO interrupt pending cleared after claim
00000000 # check no interrupts pending
00000000 # read sip (7.4)
00000408 # check GPIO and UART interrupt pending on intPending0
00000000 # nothing in claim register
00000408 # check GPIO and UART interrupt pending on intPending0
00000000 # check no interrupts pending
00000200 # read sip (7.5)
00000408 # check GPIO and UART interrupt pending on intPending0
00000003 # claim gives 3 for ID of GPIO
00000400 # check GPIO interrupt pending cleared after claim
00000000 # check no interrupts pending
00000000 # read sip (7.6)
00000408 # check GPIO and UART interrupt pending on intPending0
00000000 # nothing in claim register
00000408 # check GPIO and UART interrupt pending on intPending0
00000000 # check no interrupts pending
00000009 # output from ecall in supervisor mode
00000800 # MEIP set (8.0)
00000408 # check GPIO and UART interrupt pending on intPending0
0000000A # claim UART
00000008 # GPIO interrupt pending after UART claimcomp
00000003 # claim gives 3 for ID of GPIO
00000000 # read empty MIP # no interrupts, meip is low
00000000 # check no interrupts pending
00000800 # MEIP set
00000008 # GPIO interrupt pending after complete
00000003 # claim gives 3 for ID of GPIO
00000000 # read empty MIP # meip is zeroed
00000000 # check no interrupts pending
00000800 # MEIP set
00000400 # check GPIO interrupt pending cleared after claim
00000800 # MEIP set
00000408 # check GPIO and UART interrupt pending on intPending0
0000000A # claim UART

0
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-plic-s-01.reference_output Normal file
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33
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-uart-01.reference_output Normal file
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@ -0,0 +1,33 @@
00000000 # Reset tests
00000001 # 00000000 *** commented because LCR should reset to zero but resets to 3 due to the FPGA
00000000
00000060
00000000
00000060 # read-write test
00000020 # transmitter register empty but shift register not
00000101 # transmitter is not empty when done transmitting 5 bits
00000000
00000060
00000101 # Multi-bit transmission: 5 bits
00000015
00000101 # Transmit 6 bits
0000002A
00000101 # Transmit 7 bits
0000007F
00000101 # Transmit 8 bits
00000080
00000002 # Transmission interrupt tests
00000401 # Interrupt generated by finished transmission
00000004
00000006 # IIR return LSR intr and LSR has an overflow error
00000063
00000004
00000001
00000001 # MODEM interrupt tests
00000000
00000011
00000001
0000000b # ecall from test termination

81
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
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@ -954,6 +954,17 @@ read08_test:
// address to read in t3, expected 8 bit value in t4 (unused, but there for your perusal). // address to read in t3, expected 8 bit value in t4 (unused, but there for your perusal).
li t2, 0xBAD // bad value that will be overwritten on good reads. li t2, 0xBAD // bad value that will be overwritten on good reads.
lb t2, 0(t3) lb t2, 0(t3)
andi t2, t2, 0xFF // mask to lower 8 bits
sw t2, 0(t1)
addi t1, t1, 4
addi a6, a6, 4
j test_loop // go to next test case
read04_test:
// address to read in t3, expected 8 bit value in t4 (unused, but there for your perusal).
li t2, 0xBAD // bad value that will be overwritten on good reads.
lb t2, 0(t3)
andi t2, t2, 15 // mask lower 4 bits
sw t2, 0(t1) sw t2, 0(t1)
addi t1, t1, 4 addi t1, t1, 4
addi a6, a6, 4 addi a6, a6, 4
@ -974,6 +985,18 @@ readsip_test: // read the MIP into the signature
j test_loop // go to next test case j test_loop // go to next test case
claim_m_plic_interrupts: // clears one non-pending PLIC interrupt claim_m_plic_interrupts: // clears one non-pending PLIC interrupt
li t2, 0x0C00000C // GPIO priority
li t3, 7
lw t4, 0(t2)
sw t3, 0(t2)
sw t4, -4(sp)
addi sp, sp, -4
li t2, 0x0C000028 // UART priority
li t3, 7
lw t4, 0(t2)
sw t3, 0(t2)
sw t4, -4(sp)
addi sp, sp, -4
li t2, 0x0C002000 li t2, 0x0C002000
li t3, 0x0C200004 li t3, 0x0C200004
li t4, 0xFFF li t4, 0xFFF
@ -982,9 +1005,28 @@ claim_m_plic_interrupts: // clears one non-pending PLIC interrupt
lw t5, 0(t3) // make PLIC claim lw t5, 0(t3) // make PLIC claim
sw t5, 0(t3) // complete claim made sw t5, 0(t3) // complete claim made
sw t6, 0(t2) // restore saved enable status sw t6, 0(t2) // restore saved enable status
li t2, 0x0C00000C // GPIO priority
li t3, 0x0C000028 // UART priority
lw t4, 4(sp) // load stored GPIO and UART priority
lw t5, 0(sp)
addi sp, sp, 8 // restore stack pointer
sw t4, 0(t2)
sw t5, 0(t3)
j test_loop j test_loop
claim_s_plic_interrupts: // clears one non-pending PLIC interrupt claim_s_plic_interrupts: // clears one non-pending PLIC interrupt
li t2, 0x0C00000C // GPIO priority
li t3, 7
lw t4, 0(t2)
sw t3, 0(t2)
sw t4, -4(sp)
addi sp, sp, -4
li t2, 0x0C000028 // UART priority
li t3, 7
lw t4, 0(t2)
sw t3, 0(t2)
sw t4, -4(sp)
addi sp, sp, -4
li t2, 0x0C002080 li t2, 0x0C002080
li t3, 0x0C201004 li t3, 0x0C201004
li t4, 0xFFF li t4, 0xFFF
@ -993,25 +1035,52 @@ claim_s_plic_interrupts: // clears one non-pending PLIC interrupt
lw t5, 0(t3) // make PLIC claim lw t5, 0(t3) // make PLIC claim
sw t5, 0(t3) // complete claim made sw t5, 0(t3) // complete claim made
sw t6, 0(t2) // restore saved enable status sw t6, 0(t2) // restore saved enable status
li t2, 0x0C00000C // GPIO priority
li t3, 0x0C000028 // UART priority
lw t4, 4(sp) // load stored GPIO and UART priority
lw t5, 0(sp)
addi sp, sp, 8 // restore stack pointer
sw t4, 0(t2)
sw t5, 0(t3)
j test_loop
uart_lsr_intr_wait: // waits for interrupts to be ready
li t2, 0x10000002 // IIR
li t4, 0x6
uart_lsr_intr_loop:
lb t3, 0(t2)
andi t3, t3, 0x7
bne t3, t4, uart_lsr_intr_loop
sw t3, 0(t1)
addi t1, t1, 4
addi a6, a6, 4
j test_loop j test_loop
uart_data_wait: uart_data_wait:
li t2, 0x10000005 // LSR li t2, 0x10000005 // LSR
li t3, 0x10000002 // IIR li t3, 0x10000002 // IIR
li a4, 0x61
uart_read_LSR_IIR:
lb t4, 0(t3) // save IIR before potential clear lb t4, 0(t3) // save IIR before potential clear
lb t5, 0(t2) lb t5, 0(t2)
andi t5, t5, 1 // only care if data is ready andi t6, t5, 0x61 // only care if all transmissions are done
li t6, 1 bne a4, t6, uart_read_LSR_IIR
beq t5, t6, uart_data_ready
j uart_data_wait
uart_data_ready: uart_data_ready:
sb t4, 0(t1) li t2, 0
sb t5, 1(t1) sw t2, 0(t1) // clear entry deadbeef from memory
andi t5, t5, 0x9F // mask THRE and TEMT from signature
sb t4, 1(t1) // IIR
sb t5, 0(t1) // LSR
addi t1, t1, 4 addi t1, t1, 4
addi a6, a6, 4 addi a6, a6, 4
j test_loop j test_loop
uart_clearmodemintr:
li t2, 0x10000006
lb t2, 0(t2)
j test_loop
goto_s_mode: goto_s_mode:
// return to address in t3, // return to address in t3,
li a0, 3 // Trap handler behavior (go to supervisor mode) li a0, 3 // Trap handler behavior (go to supervisor mode)

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///////////////////////////////////////////
//
// WALLY-plic
//
// Author: David_Harris@hmc.edu and Nicholas Lucio <nlucio@hmc.edu>
//
// Created 2022-06-16
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
#include "WALLY-TEST-LIB-32.h"
INIT_TESTS
TRAP_HANDLER m
j run_test_loop // begin test loop/table tests instead of executing inline code.
INIT_TEST_TABLE
END_TESTS
TEST_STACK_AND_DATA
.align 2
test_cases:
# ---------------------------------------------------------------------------------------------
# Test Contents
#
# Here is where the actual tests are held, or rather, what the actual tests do.
# each entry consists of 3 values that will be read in as follows:
#
# '.4byte [x28 Value], [x29 Value], [x30 value]'
# or
# '.4byte [address], [value], [test type]'
#
# The encoding for x30 test type values can be found in the test handler in the framework file
#
# ---------------------------------------------------------------------------------------------
# =========== Define PLIC registers ===========
.equ PLIC, 0x0C000000
.equ PLIC_INTPRI_GPIO, (PLIC+0x00000C) # GPIO is interrupt 3
.equ PLIC_INTPRI_UART, (PLIC+0x000028) # UART is interrupt 10
.equ PLIC_INTPENDING0, (PLIC+0x001000) # intPending0 register
.equ PLIC_INTEN00, (PLIC+0x002000) # interrupt enables for context 0 (machine mode) sources 31:1
.equ PLIC_INTEN10, (PLIC+0x002080) # interrupt enables for context 1 (supervisor mode) sources 31:1
.equ PLIC_THRESH0, (PLIC+0x200000) # Priority threshold for context 0 (machine mode)
.equ PLIC_CLAIM0, (PLIC+0x200004) # Claim/Complete register for context 0
.equ PLIC_THRESH1, (PLIC+0x201000) # Priority threshold for context 1 (supervisor mode)
.equ PLIC_CLAIM1, (PLIC+0x201004) # Claim/Complete register for context 1
# =========== Define GPIO registers ===========
.equ GPIO, 0x10060000
.equ input_val, (GPIO+0x00)
.equ input_en, (GPIO+0x04)
.equ output_en, (GPIO+0x08)
.equ output_val, (GPIO+0x0C)
.equ rise_ie, (GPIO+0x18)
.equ rise_ip, (GPIO+0x1C)
.equ fall_ie, (GPIO+0x20)
.equ fall_ip, (GPIO+0x24)
.equ high_ie, (GPIO+0x28)
.equ high_ip, (GPIO+0x2C)
.equ low_ie, (GPIO+0x30)
.equ low_ip, (GPIO+0x34)
.equ iof_en, (GPIO+0x38)
.equ iof_sel, (GPIO+0x3C)
.equ out_xor, (GPIO+0x40)
# =========== Define UART registers ===========
.equ UART, 0x10000000
.equ UART_IER, (UART+0x01)
.equ UART_MCR, (UART+0x04)
.equ UART_MSR, (UART+0x06)
# =========== Initialize UART and GPIO ===========
# GPIO Initialization
.4byte input_en, 0x00000001, write32_test # enable bit 0 of input_en
.4byte output_en, 0x00000001, write32_test # enable bit 0 of output_en
.4byte output_val, 0x00000000, write32_test # make sure output_val is 0
.4byte rise_ie, 0x00000001, write32_test # enable rise interrupts
# =========== Initialize relevant PLIC registers ===========
.4byte PLIC_INTPRI_GPIO, 0x00000000, write32_test # set GPIO priority to zero
.4byte PLIC_INTPRI_UART, 0x00000000, write32_test # set UART priority to zero
.4byte PLIC_INTEN00, 0x00000408, write32_test # enable m-mode interrupts
.4byte PLIC_INTEN10, 0x00000408, write32_test # enable s-mode interrupts
.4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0
.4byte PLIC_THRESH1, 0x00000007, write32_test # set s-mode threshold to max
# =========== Machine-Mode Priority Testing (1.T.X) ===========
# Test 1.0.0: GPIO int lacks priority (0 = 0)
.4byte PLIC_THRESH0, 0x00000000, write32_test # change threshold
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
.4byte 0x0, 0x00000000, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
.4byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear interrupt
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim
.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
# Test 1.0.1: GPIO int has priority (1 > 0)
.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # let GPIO cause interrupts
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
.4byte 0x0, 0x00000800, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear interrupt
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim
.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
# Test 1.0.2: meip and c/c clear without interrupt pending
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear interrupt
.4byte 0x0, 0x00000000, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # expect no interrupt pending
.4byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear interrupt
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim
.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
# Test 1.1.0: GPIO lacks priority (1 = 1)
.4byte PLIC_THRESH0, 0x00000001, write32_test # change threshold
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
.4byte 0x0, 0x00000000, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear interrupt
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier
.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
# Test 1.1.1: GPIO int has priority (2 > 1)
.4byte PLIC_INTPRI_GPIO, 0x00000002, write32_test # let GPIO cause interrupts
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
.4byte 0x0, 0x00000800, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear interrupt
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim
.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
# Test 1.2.0: GPIO int lacks priority (2 = 2)
.4byte PLIC_THRESH0, 0x00000002, write32_test # change threshold
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
.4byte 0x0, 0x00000000, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear interrupt
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier
.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
# Test 1.2.1: GPIO int has priority (3 > 2)
.4byte PLIC_INTPRI_GPIO, 0x00000003, write32_test # let GPIO cause interrupts
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
.4byte 0x0, 0x00000800, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear interrupt
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim
.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
# Test 1.3.0: GPIO int lacks priority (3 = 3)
.4byte PLIC_THRESH0, 0x00000003, write32_test # change threshold
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
.4byte 0x0, 0x00000000, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear interrupt
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier
.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
# Test 1.3.1: GPIO int has priority (4 > 3)
.4byte PLIC_INTPRI_GPIO, 0x00000004, write32_test # let GPIO cause interrupts
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
.4byte 0x0, 0x00000800, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear interrupt
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim
.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
# Test 1.4.0: GPIO int lacks priority (4 = 4)
.4byte PLIC_THRESH0, 0x00000004, write32_test # change threshold
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
.4byte 0x0, 0x00000000, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear interrupt
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier
.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
# Test 1.4.1: GPIO int has priority (5 > 4)
.4byte PLIC_INTPRI_GPIO, 0x00000005, write32_test # let GPIO cause interrupts
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
.4byte 0x0, 0x00000800, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear interrupt
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim
.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
# Test 1.5.0: GPIO int lacks priority (5 = 5)
.4byte PLIC_THRESH0, 0x00000005, write32_test # change threshold
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
.4byte 0x0, 0x00000000, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear interrupt
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier
.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
# Test 1.5.1: GPIO int has priority (6 > 5)
.4byte PLIC_INTPRI_GPIO, 0x00000006, write32_test # let GPIO cause interrupts
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
.4byte 0x0, 0x00000800, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear interrupt
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim
.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
# Test 1.6.0: GPIO int lacks priority (6 = 6)
.4byte PLIC_THRESH0, 0x00000006, write32_test # change threshold
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
.4byte 0x0, 0x00000000, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear interrupt
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier
.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
# Test 1.6.1: GPIO int has priority (7 > 6)
.4byte PLIC_INTPRI_GPIO, 0x00000007, write32_test # let GPIO cause interrupts
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
.4byte 0x0, 0x00000800, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear interrupt
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim
.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
# Test 1.7.0: GPIO int lacks priority (7 = 7)
.4byte PLIC_THRESH0, 0x00000007, write32_test # change threshold
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
.4byte 0x0, 0x00000000, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear interrupt
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier
.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
# =========== UART vs GPIO priority (2.X) ===========
.4byte PLIC_INTEN00, 0x00000408, write32_test # enable m-mode interrupts
.4byte PLIC_INTEN10, 0x00000408, write32_test # enable s-mode interrupts
.4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0
.4byte PLIC_THRESH1, 0x00000007, write32_test # set s-mode threshold to max
# UART Initialization
.4byte UART_IER, 0x08, write08_test # enable modem status interrupts from CTS
.4byte UART_MCR, 0x10, write08_test # enable loopback mode, RTS = 0
.4byte UART_MSR, 0x00, write08_test # disable UART interrupt
# Test 2.0: GPIO Priority = UART Priority
.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1
.4byte PLIC_INTPRI_UART, 0x00000001, write32_test # UARTPriority = 1
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
.4byte 0x0, 0x00000800, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
# Test 2.1: GPIO Priority > UART Priority
.4byte PLIC_INTPRI_GPIO, 0x00000003, write32_test # GPIOPriority = 3
.4byte PLIC_INTPRI_UART, 0x00000002, write32_test # UARTPriority = 2
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
.4byte 0x0, 0x00000800, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
# Test 2.2: GPIO Priority < UART Priority
.4byte PLIC_INTPRI_GPIO, 0x00000004, write32_test # GPIOPriority = 4
.4byte PLIC_INTPRI_UART, 0x00000005, write32_test # UARTPriority = 5
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
.4byte 0x0, 0x00000800, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
.4byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for UART
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
.4byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
# Test 2.3: GPIO Priority < UART Priority
.4byte PLIC_INTPRI_GPIO, 0x00000006, write32_test # GPIOPriority = 6
.4byte PLIC_INTPRI_UART, 0x00000007, write32_test # UARTPriority = 7
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
.4byte 0x0, 0x00000800, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
.4byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for UART
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
.4byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
# Test 2.4: Interrupts don't have enough priority
.4byte PLIC_INTPRI_GPIO, 0x00000004, write32_test # GPIOPriority = 4
.4byte PLIC_INTPRI_UART, 0x00000005, write32_test # UARTPriority = 5
.4byte PLIC_THRESH0, 0x00000006, write32_test # set m-mode threshold to 6
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
.4byte 0x0, 0x00000000, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
.4byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for GPIO
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
.4byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
# =========== SEIP tests (3.X) ===========
.4byte PLIC_INTEN00, 0x00000408, write32_test # enable m-mode interrupts
.4byte PLIC_INTEN10, 0x00000408, write32_test # enable s-mode interrupts
.4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0
.4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0
# Test 3.0: Cause machine and supervisor interrupts
.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1
.4byte PLIC_INTPRI_UART, 0x00000001, write32_test # UARTPriority = 1
.4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0
.4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
.4byte 0x0, 0x00000A00, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
# Test 3.1: Suppress machine mode interrupts
.4byte PLIC_INTPRI_GPIO, 0x00000003, write32_test # GPIOPriority = 3
.4byte PLIC_INTPRI_UART, 0x00000002, write32_test # UARTPriority = 2
.4byte PLIC_THRESH0, 0x00000007, write32_test # set m-mode threshold to 7
.4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
.4byte 0x0, 0x00000200, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
# Test 3.2: Cause SEIP with UART first
.4byte PLIC_INTPRI_GPIO, 0x00000006, write32_test # GPIOPriority = 6
.4byte PLIC_INTPRI_UART, 0x00000007, write32_test # UARTPriority = 7
.4byte PLIC_THRESH0, 0x00000007, write32_test # set m-mode threshold to 7
.4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
.4byte 0x0, 0x00000200, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
.4byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for GPIO
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
.4byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
# Test 3.3: Low SEIP due to insufficient priority
.4byte PLIC_INTPRI_GPIO, 0x00000002, write32_test # GPIOPriority = 2
.4byte PLIC_INTPRI_UART, 0x00000003, write32_test # UARTPriority = 3
.4byte PLIC_THRESH0, 0x00000004, write32_test # set m-mode threshold to 4
.4byte PLIC_THRESH1, 0x00000005, write32_test # set s-mode threshold to 5
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
.4byte 0x0, 0x00000000, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
.4byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending cleared for GPIO
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
.4byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
# =========== UART interrupt enable tests (4.X) ===========
.4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0
.4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0
.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIO Priority = 1
.4byte PLIC_INTPRI_UART, 0x00000001, write32_test # UART Priority = 1
# Test 4.0: GPIO m-mode disabled
.4byte PLIC_INTEN00, 0x00000400, write32_test # disable GPIO m-mode interrupts
.4byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
.4byte 0x0, 0x00000A00, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART
.4byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
.4byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
# Test 4.1: UART m-mode disabled
.4byte PLIC_INTEN00, 0x00000008, write32_test # disable UART m-mode interrupts
.4byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
.4byte 0x0, 0x00000200, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART
.4byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
.4byte PLIC_CLAIM0, 0x00000000, write32_test # complete claim made earlier
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
# Test 4.2: GPIO s-mode disabled
.4byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts
.4byte PLIC_INTEN10, 0x00000400, write32_test # enable all s-mode interrupts
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
.4byte 0x0, 0x00000A00, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART
.4byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
.4byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
# Test 4.3: UART s-mode disabled
.4byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts
.4byte PLIC_INTEN10, 0x00000008, write32_test # enable all s-mode interrupts
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
.4byte 0x0, 0x00000800, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART
.4byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
.4byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
# Test 4.4: GPIO and UART s-mode disabled
.4byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts
.4byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
.4byte 0x0, 0x00000800, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART
.4byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
.4byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
# Test 4.5: GPIO and UART m-mode disabled
.4byte PLIC_INTEN00, 0x00000000, write32_test # disable GPIO interrupts
.4byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
.4byte 0x0, 0x00000200, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART
.4byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
.4byte PLIC_CLAIM0, 0x00000000, write32_test # complete claim made earlier
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
# Test 4.6: GPIO and UART fully disabled
.4byte PLIC_INTEN00, 0x00000000, write32_test # disable GPIO interrupts
.4byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
.4byte 0x0, 0x00000200, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART
.4byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
.4byte PLIC_CLAIM0, 0x00000000, write32_test # complete claim made earlier
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
# =========== GPIO interrupt enable tests (5.X) ===========
.4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0
.4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0
.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIO Priority = 1
.4byte PLIC_INTPRI_UART, 0x00000001, write32_test # UART Priority = 1
# Test 5.0: GPIO m-mode disabled
.4byte PLIC_INTEN00, 0x00000400, write32_test # disable GPIO m-mode interrupts
.4byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
.4byte 0x0, 0x00000200, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART
.4byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for GPIO
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
.4byte PLIC_CLAIM0, 0x00000000, write32_test # complete claim made earlier
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
# Test 5.1: UART m-mode disabled
.4byte PLIC_INTEN00, 0x00000008, write32_test # disable UART m-mode interrupts
.4byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
.4byte 0x0, 0x00000A00, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
# Test 5.2: GPIO s-mode disabled
.4byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts
.4byte PLIC_INTEN10, 0x00000400, write32_test # enable all s-mode interrupts
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
.4byte 0x0, 0x00000800, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
# Test 5.3: UART s-mode disabled
.4byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts
.4byte PLIC_INTEN10, 0x00000008, write32_test # enable all s-mode interrupts
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
.4byte 0x0, 0x00000A00, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
# Test 5.4: GPIO and UART s-mode disabled
.4byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts
.4byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
.4byte 0x0, 0x00000800, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART
.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
# Test 5.5: GPIO and UART m-mode disabled
.4byte PLIC_INTEN00, 0x00000000, write32_test # disable GPIO interrupts
.4byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
.4byte 0x0, 0x00000200, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART
.4byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
.4byte PLIC_CLAIM0, 0x00000000, write32_test # complete claim made earlier
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
# Test 5.6: GPIO and UART fully disabled
.4byte PLIC_INTEN00, 0x00000000, write32_test # disable GPIO interrupts
.4byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
.4byte 0x0, 0x00000000, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART
.4byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
.4byte PLIC_CLAIM0, 0x00000000, write32_test # complete claim made earlier
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one
.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one
.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
# =========== S-mode enable tests (7.X) ===========
.4byte 0x0, 0x0, goto_s_mode # go to s-mode. 0xb written to output
.4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0
.4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0
.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIO Priority = 1
.4byte PLIC_INTPRI_UART, 0x00000001, write32_test # UART Priority = 1
# Test 7.0: GPIO m-mode disabled
.4byte PLIC_INTEN00, 0x00000400, write32_test # disable GPIO m-mode interrupts
.4byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
.4byte 0x0, 0x00000200, readsip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
.4byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
.4byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier
.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one
.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
# Test 7.1: UART m-mode disabled
.4byte PLIC_INTEN00, 0x00000008, write32_test # disable UART m-mode interrupts
.4byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
.4byte 0x0, 0x00000200, readsip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
.4byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
.4byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier
.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one
.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
# Test 7.2: GPIO s-mode disabled
.4byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts
.4byte PLIC_INTEN10, 0x00000400, write32_test # enable all s-mode interrupts
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
.4byte 0x0, 0x00000200, readsip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
.4byte PLIC_CLAIM1, 0x0000000A, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for GPIO
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
.4byte PLIC_CLAIM1, 0x0000000A, write32_test # complete claim made earlier
.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one
.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
# Test 7.3: UART s-mode disabled
.4byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts
.4byte PLIC_INTEN10, 0x00000008, write32_test # enable all s-mode interrupts
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
.4byte 0x0, 0x00000200, readsip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
.4byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
.4byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier
.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one
.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
# Test 7.4: GPIO and UART s-mode disabled
.4byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts
.4byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
.4byte 0x0, 0x00000000, readsip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
.4byte PLIC_CLAIM1, 0x00000000, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending cleared for GPIO
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
.4byte PLIC_CLAIM1, 0x00000000, write32_test # complete claim made earlier
.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one
.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
# Test 7.5: GPIO and UART m-mode disabled
.4byte PLIC_INTEN00, 0x00000000, write32_test # disable GPIO interrupts
.4byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
.4byte 0x0, 0x00000200, readsip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
.4byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
.4byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier
.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one
.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
# Test 7.6: GPIO and UART fully disabled
.4byte PLIC_INTEN00, 0x00000000, write32_test # disable GPIO interrupts
.4byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
.4byte 0x0, 0x00000000, readsip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
.4byte PLIC_CLAIM1, 0x00000000, read32_test # read claim register
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending cleared for GPIO
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
.4byte PLIC_CLAIM1, 0x00000000, write32_test # complete claim made earlier
.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one
.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending
# =========== Special claim tests (8) ===========
.4byte 0x0, 0x0, goto_m_mode # write 0x9 to output
.4byte PLIC_INTPRI_GPIO, 0x00000006, write32_test # GPIO Priority = 6
.4byte PLIC_INTPRI_UART, 0x00000007, write32_test # UART Priority = 7
.4byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts
.4byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts
.4byte PLIC_THRESH0, 0x00000005, write32_test # set m-mode threshold to 5
# Test 8
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt
.4byte 0x0, 0x00000800, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # read interrupt pending
.4byte PLIC_CLAIM0, 0x0000000A, read32_test # claim UART
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # UART interrupt cleared
.4byte PLIC_CLAIM0, 0x00000003, read32_test # claim GPIO
.4byte 0x0, 0x00000000, readmip_test # no interrupts, meip is low
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # both interrupts claimed
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete GPIO
.4byte 0x0, 0x00000800, readmip_test # GPIO interrupt sets MEIP
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # GPIO bit is set
.4byte PLIC_CLAIM0, 0x00000003, read32_test # claim GPIO again
.4byte 0x0, 0x00000000, readmip_test # meip is zeroed
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # both interrupts claimed
.4byte PLIC_CLAIM0, 0x0000000A, write32_test # complete UART claim
.4byte 0x0, 0x00000800, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000400, read32_test # UART pending
.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete GPIO claim
.4byte 0x0, 0x00000800, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000408, read32_test # GPIO and UART pending
.4byte PLIC_CLAIM0, 0x0000000A, read32_test # claim UART
.4byte 0x0, 0x0, terminate_test # terminate tests

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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-s-01.S Normal file
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///////////////////////////////////////////
//
// WALLY-gpio
//
// Author: David_Harris@hmc.edu and Nicholas Lucio <nlucio@hmc.edu>
//
// Created 2022-06-16
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
#include "WALLY-TEST-LIB-32.h"
INIT_TESTS
TRAP_HANDLER m
j run_test_loop // begin test loop/table tests instead of executing inline code.
INIT_TEST_TABLE
END_TESTS
TEST_STACK_AND_DATA
.align 2
test_cases:
# ---------------------------------------------------------------------------------------------
# Test Contents
#
# Here is where the actual tests are held, or rather, what the actual tests do.
# each entry consists of 3 values that will be read in as follows:
#
# '.4byte [x28 Value], [x29 Value], [x30 value]'
# or
# '.4byte [address], [value], [test type]'
#
# The encoding for x30 test type values can be found in the test handler in the framework file
#
# ---------------------------------------------------------------------------------------------
# =========== Define PLIC registers ===========
.equ PLIC, 0x0C000000
.equ PLIC_INTPRI_GPIO, (PLIC+0x00000C) # GPIO is interrupt 3
.equ PLIC_INTPRI_UART, (PLIC+0x000028) # UART is interrupt 10
.equ PLIC_INTPENDING0, (PLIC+0x001000) # intPending0 register
.equ PLIC_INTEN00, (PLIC+0x002000) # interrupt enables for context 0 (machine mode) sources 31:1
.equ PLIC_INTEN10, (PLIC+0x002080) # interrupt enables for context 1 (supervisor mode) sources 31:1
.equ PLIC_THRESH0, (PLIC+0x200000) # Priority threshold for context 0 (machine mode)
.equ PLIC_CLAIM0, (PLIC+0x200004) # Claim/Complete register for context 0
.equ PLIC_THRESH1, (PLIC+0x201000) # Priority threshold for context 1 (supervisor mode)
.equ PLIC_CLAIM1, (PLIC+0x201004) # Claim/Complete register for context 1
# =========== Define GPIO registers ===========
.equ GPIO, 0x10060000
.equ input_val, (GPIO+0x00)
.equ input_en, (GPIO+0x04)
.equ output_en, (GPIO+0x08)
.equ output_val, (GPIO+0x0C)
.equ rise_ie, (GPIO+0x18)
.equ rise_ip, (GPIO+0x1C)
.equ fall_ie, (GPIO+0x20)
.equ fall_ip, (GPIO+0x24)
.equ high_ie, (GPIO+0x28)
.equ high_ip, (GPIO+0x2C)
.equ low_ie, (GPIO+0x30)
.equ low_ip, (GPIO+0x34)
.equ iof_en, (GPIO+0x38)
.equ iof_sel, (GPIO+0x3C)
.equ out_xor, (GPIO+0x40)
# =========== Define UART registers ===========
.equ UART, 0x10000000
.equ UART_IER, (UART+0x01)
.equ UART_MCR, (UART+0x04)
.equ UART_MSR, (UART+0x06)
# =========== Initialize UART and GPIO ===========
# GPIO Initialization
.4byte input_en, 0x00000001, write32_test # enable bit 0 of input_en
.4byte output_en, 0x00000001, write32_test # enable bit 0 of output_en
.4byte output_val, 0x00000000, write32_test # make sure output_val is 0
.4byte rise_ie, 0x00000001, write32_test # enable rise interrupts
# UART Initialization
.4byte UART_IER, 0x08, write08_test # enable modem status interrupts from CTS
.4byte UART_MCR, 0x10, write08_test # enable loopback mode, RTS = 0
.4byte UART_MSR, 0x00, write08_test # disable UART interrupt
# =========== Initialize relevant PLIC registers ===========
.4byte PLIC_INTPRI_GPIO, 0x00000000, write32_test # set GPIO priority to zero
.4byte PLIC_INTPRI_UART, 0x00000000, write32_test # set UART priority to zero
.4byte PLIC_INTEN00, 0x00000408, write32_test # enable m-mode interrupts
.4byte PLIC_INTEN10, 0x00000408, write32_test # enable s-mode interrupts
.4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0
.4byte PLIC_THRESH1, 0x00000007, write32_test # set s-mode threshold to max
# =========== Machine-Mode Priority Testing (1.T.X) ===========
# Test 1.0.0: GPIO int lacks priority (0 = 0)
.4byte PLIC_THRESH0, 0x00000000, write32_test # change threshold
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
.4byte 0x0, 0x00000000, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect no interrupt pending *** pending bug?????
.4byte 0x0, 0x00000000, readmclaimcomplete_test # read and clear claimcomplete
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000000, write32_test # clear interrupt
# Test 1.0.1: GPIO int has priority (1 > 0)
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # let GPIO cause interrupts
.4byte 0x0, 0x00000800, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
.4byte 0x0, 0x00000003, readmclaimcomplete_test # read and clear claimcomplete
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000000, write32_test # clear interrupt
# Test 1.0.2: meip and c/c clear without interrupt pending
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000000, write32_test # clear interrupt
.4byte 0x0, 0x00000000, readmip_test # read mip
.4byte 0x0, 0x00000000, readmclaimcomplete_test # read and clear claimcomplete
# Test 1.1.0: GPIO lacks priority (1 = 1)
.4byte PLIC_THRESH0, 0x00000001, write32_test # change threshold
.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
.4byte 0x0, 0x00000000, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # expect no interrupt pending
.4byte 0x0, 0x00000000, readmclaimcomplete_test # read and clear claimcomplete
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000000, write32_test # clear interrupt
# Test 1.1.1: GPIO int has priority (2 > 1)
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
.4byte PLIC_INTPRI_GPIO, 0x00000002, write32_test # let GPIO cause interrupts
.4byte 0x0, 0x00000800, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
.4byte 0x0, 0x00000003, readmclaimcomplete_test # read and clear claimcomplete
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000000, write32_test # clear interrupt
# Test 1.2.0: GPIO int lacks priority (2 = 2)
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
.4byte PLIC_THRESH0, 0x00000002, write32_test # change threshold
.4byte 0x0, 0x00000000, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # expect no interrupt pending
.4byte 0x0, 0x00000000, readmclaimcomplete_test # read and clear claimcomplete
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000000, write32_test # clear interrupt
# Test 1.2.1: GPIO int has priority (3 > 2)
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
.4byte PLIC_INTPRI_GPIO, 0x00000003, write32_test # let GPIO cause interrupts
.4byte 0x0, 0x00000800, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
.4byte 0x0, 0x00000003, readmclaimcomplete_test # read and clear claimcomplete
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000000, write32_test # clear interrupt
# Test 1.3.0: GPIO int lacks priority (3 = 3)
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
.4byte PLIC_THRESH0, 0x00000003, write32_test # change threshold
.4byte 0x0, 0x00000000, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # expect no interrupt pending
.4byte 0x0, 0x00000000, readmclaimcomplete_test # read and clear claimcomplete
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000000, write32_test # clear interrupt
# Test 1.3.1: GPIO int has priority (4 > 3)
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
.4byte PLIC_INTPRI_GPIO, 0x00000004, write32_test # let GPIO cause interrupts
.4byte 0x0, 0x00000800, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
.4byte 0x0, 0x00000003, readmclaimcomplete_test # read and clear claimcomplete
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000000, write32_test # clear interrupt
# Test 1.4.0: GPIO int lacks priority (4 = 4)
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
.4byte PLIC_THRESH0, 0x00000004, write32_test # change threshold
.4byte 0x0, 0x00000000, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # expect no interrupt pending
.4byte 0x0, 0x00000000, readmclaimcomplete_test # read and clear claimcomplete
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000000, write32_test # clear interrupt
# Test 1.4.1: GPIO int has priority (5 > 4)
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
.4byte PLIC_INTPRI_GPIO, 0x00000005, write32_test # let GPIO cause interrupts
.4byte 0x0, 0x00000800, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
.4byte 0x0, 0x00000003, readmclaimcomplete_test # read and clear claimcomplete
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000000, write32_test # clear interrupt
# Test 1.5.0: GPIO int lacks priority (5 = 5)
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
.4byte PLIC_THRESH0, 0x00000005, write32_test # change threshold
.4byte 0x0, 0x00000000, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # expect no interrupt pending
.4byte 0x0, 0x00000000, readmclaimcomplete_test # read and clear claimcomplete
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000000, write32_test # clear interrupt
# Test 1.5.1: GPIO int has priority (6 > 5)
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
.4byte PLIC_INTPRI_GPIO, 0x00000006, write32_test # let GPIO cause interrupts
.4byte 0x0, 0x00000800, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
.4byte 0x0, 0x00000003, readmclaimcomplete_test # read and clear claimcomplete
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000000, write32_test # clear interrupt
# Test 1.6.0: GPIO int lacks priority (6 = 6)
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
.4byte PLIC_THRESH0, 0x00000006, write32_test # change threshold
.4byte 0x0, 0x00000000, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # expect no interrupt pending
.4byte 0x0, 0x00000000, readmclaimcomplete_test # read and clear claimcomplete
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000000, write32_test # clear interrupt
# Test 1.6.1: GPIO int has priority (7 > 6)
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
.4byte PLIC_INTPRI_GPIO, 0x00000007, write32_test # let GPIO cause interrupts
.4byte 0x0, 0x00000800, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
.4byte 0x0, 0x00000003, readmclaimcomplete_test # read and clear claimcomplete
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000000, write32_test # clear interrupt
# Test 1.7.0: GPIO int lacks priority (7 = 7)
.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
.4byte PLIC_THRESH0, 0x00000007, write32_test # change threshold
.4byte 0x0, 0x00000000, readmip_test # read mip
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # expect no interrupt pending
.4byte 0x0, 0x00000000, readmclaimcomplete_test # read and clear claimcomplete
.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
.4byte output_val, 0x00000000, write32_test # clear output_val
.4byte rise_ip, 0x00000000, write32_test # clear interrupt
# # =========== UART vs GPIO priority (2.X) =========== ***
# .4byte PLIC_INTEN00, 0x00000408, write32_test # enable m-mode interrupts
# .4byte PLIC_INTEN10, 0x00000408, write32_test # enable s-mode interrupts
# .4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0
# .4byte PLIC_THRESH1, 0x00000007, write32_test # set s-mode threshold to max
# # Test 2.0: GPIO Priority = UART Priority
# .4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
# .4byte UART_MSR, 0x00000010, write08_test # step 1 of UART interrupt
# .4byte UART_MSR, 0x00000012, write08_test # step 2 of UART interrupt
# .4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1
# .4byte PLIC_INTPRI_UART, 0x00000001, write32_test # UARTPriority = 1
# .4byte 0x0, 0x00000800, readmip_test # read mip
# .4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
# .4byte 0x0, 0x00000003, readmclaimcomplete_test # GPIO claim/complete process
# .4byte PLIC_INTPENDING0, 0x00000200, read32_test # GPIO interrupt was cleared
# .4byte 0x0, 0x00000800, readmip_test # expect mip to remain high
# .4byte 0x0, 0x0000000A, readmclaimcomplete_test # UART claim/complete process
# .4byte PLIC_INTPENDING0, 0x00000000, read32_test # UART interrupt pending was cleared
# .4byte output_val, 0x00000000, write32_test # clear output_val
# .4byte rise_ip, 0x00000000, write32_test # clear GPIO interrupt
# .4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
# # Test 2.1: GPIO Priority < UART Priority
# .4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
# .4byte UART_MSR, 0x00000010, write08_test # step 1 of UART interrupt
# .4byte UART_MSR, 0x00000012, write08_test # step 2 of UART interrupt
# .4byte PLIC_INTPRI_GPIO, 0x00000002, write32_test # GPIO Priority = 2
# .4byte PLIC_INTPRI_UART, 0x00000003, write32_test # UART Priority = 3
# .4byte 0x0, 0x00000800, readmip_test # read mip
# .4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for UART and GPIO
# .4byte 0x0, 0x0000000A, readmclaimcomplete_test # UART claim/complete process
# .4byte PLIC_INTPENDING0, 0x00000008, read32_test # UART interrupt was cleared
# .4byte 0x0, 0x00000800, readmip_test # expect mip to remain high
# .4byte 0x0, 0x00000003, readmclaimcomplete_test # GPIO claim/complete process
# .4byte PLIC_INTPENDING0, 0x00000000, read32_test # GPIO interrupt pending was cleared
# .4byte output_val, 0x00000000, write32_test # clear output_val
# .4byte rise_ip, 0x00000000, write32_test # clear GPIO interrupt
# .4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
# # Test 2.2: GPIO Priority > UART Priority
# .4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
# .4byte UART_MSR, 0x00000010, write08_test # step 1 of UART interrupt
# .4byte UART_MSR, 0x00000012, write08_test # step 2 of UART interrupt
# .4byte PLIC_INTPRI_GPIO, 0x00000005, write32_test # GPIO Priority = 5
# .4byte PLIC_INTPRI_UART, 0x00000004, write32_test # UART Priority = 4
# .4byte 0x0, 0x00000800, readmip_test # read mip
# .4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
# .4byte 0x0, 0x00000003, readmclaimcomplete_test # GPIO claim/complete process
# .4byte PLIC_INTPENDING0, 0x00000200, read32_test # GPIO interrupt was cleared
# .4byte 0x0, 0x00000800, readmip_test # expect mip to remain high
# .4byte 0x0, 0x0000000A, readmclaimcomplete_test # UART claim/complete process
# .4byte PLIC_INTPENDING0, 0x00000000, read32_test # UART interrupt pending was cleared
# .4byte output_val, 0x00000000, write32_test # clear output_val
# .4byte rise_ip, 0x00000000, write32_test # clear GPIO interrupt
# .4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
# # Test 2.3: GPIO Priority < UART Priority (2)
# .4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
# .4byte UART_MSR, 0x00000010, write08_test # step 1 of UART interrupt
# .4byte UART_MSR, 0x00000012, write08_test # step 2 of UART interrupt
# .4byte PLIC_INTPRI_GPIO, 0x00000006, write32_test # GPIO Priority = 6
# .4byte PLIC_INTPRI_UART, 0x00000007, write32_test # UART Priority = 7
# .4byte 0x0, 0x00000800, readmip_test # read mip
# .4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for UART and GPIO
# .4byte 0x0, 0x0000000A, readmclaimcomplete_test # UART claim/complete process
# .4byte PLIC_INTPENDING0, 0x00000008, read32_test # UART interrupt was cleared
# .4byte 0x0, 0x00000800, readmip_test # expect mip to remain high
# .4byte 0x0, 0x00000003, readmclaimcomplete_test # GPIO claim/complete process
# .4byte PLIC_INTPENDING0, 0x00000000, read32_test # GPIO interrupt pending was cleared
# .4byte output_val, 0x00000000, write32_test # clear output_val
# .4byte rise_ip, 0x00000000, write32_test # clear GPIO interrupt
# .4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
# # Test 2.4: Interrupts disabled (Thresh0 = 7)
# .4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
# .4byte UART_MSR, 0x00000010, write08_test # step 1 of UART interrupt
# .4byte UART_MSR, 0x00000012, write08_test # step 2 of UART interrupt
# .4byte PLIC_THRESH0, 0x00000007, write32_test # Disable m-mode interrupts
# .4byte PLIC_INTPRI_GPIO, 0x00000007, write32_test # GPIO Priority = 7
# .4byte PLIC_INTPRI_UART, 0x00000007, write32_test # UART Priority = 7
# .4byte 0x0, 0x00000000, readmip_test, # read mip
# .4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
# .4byte 0x0, 0x00000000, readmclaimcomplete_test # no interrupt pending
# .4byte output_val, 0x00000000, write32_test # clear output_val
# .4byte rise_ip, 0x00000000, write32_test # clear GPIO interrupt
# .4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
# # =========== SEIP tests (3.X) ===========
# .4byte PLIC_INTEN00, 0x00000408, write32_test # enable m-mode interrupts
# .4byte PLIC_INTEN10, 0x00000408, write32_test # enable s-mode interrupts
# .4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0
# .4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0
# # Test 3.0: Cause machine and supervisor interrupts
# .4byte output_val, 0x00000000, write32_test # cause rise_ip to go high
# .4byte UART_MSR, 0x00000010, write08_test # step 1 of UART interrupt
# .4byte UART_MSR, 0x00000012, write08_test # step 2 of UART interrupt
# .4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIO Priority = 1
# .4byte PLIC_INTPRI_UART, 0x00000001, write32_test # UART Priority = 1
# .4byte 0x0, 0x00000A00, readmip_test # Expect high on MEIP and SEIP
# .4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
# .4byte 0x0, 0x00000003, readmclaimcomplete_test # Expect GPIO on claim/complete
# .4byte 0x0, 0x00000A00, readmip_test # Still expect high on MEIP and SEIP
# .4byte PLIC_INTPENDING0, 0x00000200, read32_test # GPIO interrupt was cleared
# .4byte 0x0, 0x0000000A, readmclaimcomplete_test # Expect UART on claim/complete
# .4byte 0x0, 0x00000000, readmip_test # all interrupts were cleared
# .4byte PLIC_INTPENDING0, 0x00000000, read32_test # Pending should also be clear
# .4byte output_val, 0x00000000, write32_test # clear output_val
# .4byte rise_ip, 0x00000000, write32_test # clear GPIO interrupt
# .4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
# # Test 3.1: Suppress machine mode interrupts
# .4byte output_val, 0x00000000, write32_test # cause rise_ip to go high
# .4byte UART_MSR, 0x00000010, write08_test # step 1 of UART interrupt
# .4byte UART_MSR, 0x00000012, write08_test # step 2 of UART interrupt
# .4byte PLIC_INTPRI_GPIO, 0x00000003, write32_test # GPIO Priority = 3
# .4byte PLIC_INTPRI_UART, 0x00000002, write32_test # UART Priority = 2
# .4byte PLIC_THRESH0, 0x00000007, write32_test # set m-mode threshold to 7
# .4byte 0x0, 0x00000200, readmip_test # Expect high on SEIP only
# .4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
# .4byte 0x0, 0x00000003, readmclaimcomplete_test # Expect GPIO on claim/complete
# .4byte 0x0, 0x00000200, readmip_test # Expect high on SEIP only
# .4byte PLIC_INTPENDING0, 0x00000200, read32_test # GPIO interrupt was cleared
# .4byte 0x0, 0x0000000A, readmclaimcomplete_test # Expect UART on claim/complete
# .4byte 0x0, 0x00000000, readmip_test # all interrupts were cleared
# .4byte PLIC_INTPENDING0, 0x00000000, read32_test # Pending should also be clear
# .4byte output_val, 0x00000000, write32_test # clear output_val
# .4byte rise_ip, 0x00000000, write32_test # clear GPIO interrupt
# .4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
# # Test 3.2: Cause SEIP with UART first
# .4byte output_val, 0x00000000, write32_test # cause rise_ip to go high
# .4byte UART_MSR, 0x00000010, write08_test # step 1 of UART interrupt
# .4byte UART_MSR, 0x00000012, write08_test # step 2 of UART interrupt
# .4byte PLIC_INTPRI_GPIO, 0x00000006, write32_test # GPIO Priority = 6
# .4byte PLIC_INTPRI_UART, 0x00000007, write32_test # UART Priority = 7
# .4byte 0x0, 0x00000200, readmip_test # Expect high on SEIP only
# .4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
# .4byte 0x0, 0x0000000A, readmclaimcomplete_test # Expect UART on claim/complete
# .4byte 0x0, 0x00000200, readmip_test # Expect high on SEIP only
# .4byte PLIC_INTPENDING0, 0x00000008, read32_test # UART interrupt was cleared
# .4byte 0x0, 0x00000003, readmclaimcomplete_test # Expect GPIO on claim/complete
# .4byte 0x0, 0x00000000, readmip_test # all interrupts were cleared
# .4byte PLIC_INTPENDING0, 0x00000000, read32_test # Pending should also be clear
# .4byte output_val, 0x00000000, write32_test # clear output_val
# .4byte rise_ip, 0x00000000, write32_test # clear GPIO interrupt
# .4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
# # Test 3.3: Low SEIP due to insufficient priority
# .4byte output_val, 0x00000000, write32_test # cause rise_ip to go high
# .4byte UART_MSR, 0x00000010, write08_test # step 1 of UART interrupt
# .4byte UART_MSR, 0x00000012, write08_test # step 2 of UART interrupt
# .4byte PLIC_INTPRI_GPIO, 0x00000002, write32_test # GPIO Priority = 2
# .4byte PLIC_INTPRI_UART, 0x00000003, write32_test # UART Priority = 3
# .4byte PLIC_THRESH0, 0x00000004, write32_test # set m-mode threshold to 7
# .4byte PLIC_THRESH1, 0x00000005, write32_test # set s-mode threshold to 7
# .4byte 0x0, 0x00000000, readmip_test # no interrupt pending
# .4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
# .4byte 0x0, 0x00000000, readmclaimcomplete_test # Expect nothing on claim/complete
# .4byte output_val, 0x00000000, write32_test # clear output_val
# .4byte rise_ip, 0x00000000, write32_test # clear GPIO interrupt
# .4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
# # =========== UART interrupt enable tests (4.X) ===========
# .4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0
# .4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0
# .4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIO Priority = 1
# .4byte PLIC_INTPRI_UART, 0x00000001, write32_test # UART Priority = 1
# # Test 4.0: GPIO m-mode disabled
# .4byte output_val, 0x00000000, write32_test # cause rise_ip to go high
# .4byte UART_MSR, 0x00000010, write08_test # step 1 of UART interrupt
# .4byte UART_MSR, 0x00000012, write08_test # step 2 of UART interrupt
# .4byte PLIC_INTEN00, 0x000000200, write32_test # GPIO m-mode interrupt disabled
# .4byte PLIC_INTEN00, 0x000000208, write32_test # No s-mode interrupt disabled
# .4byte 0x0, 0x00000A00, readmip_test # Expect high on MEIP from UART and SEIP from GPIO
# .4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
# .4byte 0x0, 0x00000003, readmclaimcomplete_test # Expect GPIO on claim/complete
# .4byte 0x0, 0x00000200, readmip_test # Expect high on MEIP and SEIP from UART
# .4byte PLIC_INTPENDING0, 0x00000200, read32_test # interrupt pending for GPIO and UART
# .4byte 0x0, 0x0000000A, readmclaimcomplete_test # Expect UART on claim/complete
# .4byte 0x0, 0x00000000, readmip_test # all interrupts were cleared
# .4byte PLIC_INTPENDING0, 0x00000000, read32_test # Pending should also be clear
# Test 4.1: UART m-mode disabled
# Test 4.2: GPIO s-mode disabled
# Test 4.3: UART s-mode disabled
# Test 4.4: GPIO and UART s-mode disabled
# Test 4.5: GPIO and UART m-mode disabled
# Test 4.6: GPIO and UART fully disabled
.4byte 0x0, 0x0, terminate_test # terminate tests

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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-01.S Normal file
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///////////////////////////////////////////
//
// WALLY-uart
//
// Author: David_Harris@hmc.edu and Nicholas Lucio <nlucio@hmc.edu>
//
// Created 2022-06-16
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
#include "WALLY-TEST-LIB-32.h"
INIT_TESTS
TRAP_HANDLER m
j run_test_loop // begin test loop/table tests instead of executing inline code.
INIT_TEST_TABLE
END_TESTS
TEST_STACK_AND_DATA
.align 2
.equ UART, 0x10000000
.equ UART_RBR, (UART)
.equ UART_THR, (UART)
.equ UART_IER, (UART+0x01)
.equ UART_IIR, (UART+0x02)
.equ UART_FCR, (UART+0x02)
.equ UART_LCR, (UART+0x03)
.equ UART_MCR, (UART+0x04)
.equ UART_LSR, (UART+0x05)
.equ UART_MSR, (UART+0x06)
.equ UART_Scr, (UART+0x07)
test_cases:
# ---------------------------------------------------------------------------------------------
# Test Contents
#
# Here is where the actual tests are held, or rather, what the actual tests do.
# each entry consists of 3 values that will be read in as follows:
#
# '.4byte [x28 Value], [x29 Value], [x30 value]'
# or
# '.4byte [address], [value], [test type]'
#
# The encoding for x30 test type values can be found in the test handler in the framework file
#
# ---------------------------------------------------------------------------------------------
# =========== UART resets to correct values on master reset ===========
.4byte UART_IER, 0x00, read08_test
.4byte UART_IIR, 0x01, read08_test # IIR resets to 1
# .4byte UART_LCR, 0x00, read08_test *** commented out because LCR should reset to zero but resets to 3
.4byte UART_MCR, 0x00, read08_test
.4byte UART_LSR, 0x60, read08_test # LSR resets with transmit status bits set
.4byte UART_MSR, 0x00, read04_test
# =========== Basic read-write ===========
.4byte UART_LCR, 0x00, write08_test # set LCR to reset value *** remove if UART resets to correct value
.4byte UART_MCR, 0x10, write08_test # put UART into loopback for MSR test
.4byte UART_LSR, 0x60, read08_test
.4byte UART_THR, 0x00, write08_test # write value to UART
.4byte UART_LSR, 0x00, read08_test # data not ready and transmitter is not empty
.4byte 0x0, 0x0101, uart_data_wait # wait for data to become ready then output IIR and LSR
.4byte UART_RBR, 0x00, read08_test # read written value
.4byte UART_LSR, 0x60, read08_test # read LSR
# =========== Different size read-write ===========
# Transmit 5 bits
.4byte UART_LCR, 0x00, write08_test # set LCR to transmit 5 bits
.4byte UART_THR, 0x55, write08_test # write value to UART
.4byte 0x0, 0x0101, uart_data_wait # wait for data to become ready then output IIR and then LSR
.4byte UART_RBR, 0x15, read08_test # read written value without bits 5-7
# Transmit 6 bits
.4byte UART_LCR, 0x01, write08_test # set LCR to transmit six bits
.4byte UART_THR, 0xAA, write08_test # write value to UART
.4byte 0x0, 0x0101, uart_data_wait # wait for data to become ready then output IIR and then LSR
.4byte UART_RBR, 0x2A, read08_test # read written value without bits 6 & 7
# Transmit 7 bits
.4byte UART_LCR, 0x02, write08_test # set LCR to transmit seven bits
.4byte UART_THR, 0xFF, write08_test # write value to UART
.4byte 0x0, 0x0101, uart_data_wait # wait for data to become ready then output IIR and then LSR
.4byte UART_RBR, 0x7F, read08_test # read written value without bit 7
# Transmit 8 bits
.4byte UART_LCR, 0x03, write08_test # set LCR to transmit seven bits
.4byte UART_THR, 0x80, write08_test # write value to UART
.4byte 0x0, 0x0101, uart_data_wait # wait for data to become ready then output IIR and then LSR
.4byte UART_RBR, 0x80, read08_test # read full written value + sign extension
# =========== Transmit-related interrupts ===========
.4byte UART_IER, 0x07, write08_test # enable data available, buffer empty, and line status interrupts
.4byte UART_IIR, 0x02, read08_test # buffer should be empty, causing interrupt
.4byte UART_THR, 0x00, write08_test # write zeroes to transmitter
.4byte 0x0, 0x0401, uart_data_wait # IIR should have data ready interrupt
.4byte UART_THR, 0x01, write08_test # write 1 to transmitter buffer
.4byte UART_IIR, 0x04, read08_test # data interrupt should still be high
.4byte 0x0, 0x06, uart_lsr_intr_wait # wait for transmission to complete, IIR should throw error due to overrun error.
.4byte UART_LSR, 0x63, read08_test # read overrun error from LSR
.4byte UART_IIR, 0x04, read08_test # check that LSR interrupt was cleared
.4byte UART_RBR, 0x01, read08_test # read previous value from UART
# =========== MODEM interrupts ===========
.4byte UART_MSR, 0x00, write08_test # clear MSR
.4byte UART_IER, 0x08, write08_test # enable MODEM Status interrupts
.4byte UART_IIR, 0x01, read08_test # no interrupts pending
.4byte UART_MCR, 0x02, write08_test # Cause DCTS interrupt
.4byte UART_IIR, 0x00, read08_test # MODEM interrupt
.4byte UART_MSR, 0x11, read08_test # Read MSR to clear interrupt
.4byte UART_IIR, 0x01, read08_test # interrupt cleared by reading MSR
.4byte 0x0, 0x0, terminate_test