From fbbba0e5c23efd67ebe6afcd5f17c70e60cce9f2 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 17 Apr 2023 18:39:25 -0500
Subject: [PATCH] Finally we are building the fpga and can view the ila. we
are getting out of reset, but we are stuck at PCM = 10b8.
---
fpga/constraints/constraints-ArtyA7.xdc | 22 +++++++++++++++-------
fpga/constraints/small-debug.xdc | 8 +-------
fpga/src/fpgaTopArtyA7.v | 9 +++++----
3 files changed, 21 insertions(+), 18 deletions(-)
diff --git a/fpga/constraints/constraints-ArtyA7.xdc b/fpga/constraints/constraints-ArtyA7.xdc
index a9b78a78d..ff2dc359b 100644
--- a/fpga/constraints/constraints-ArtyA7.xdc
+++ b/fpga/constraints/constraints-ArtyA7.xdc
@@ -10,7 +10,7 @@ set_property PACKAGE_PIN E3 [get_ports {default_100mhz_clk}]
set_property IOSTANDARD LVCMOS33 [get_ports {default_100mhz_clk}]
##### GPI ####
-set_property PACKAGE_PIN D9 [get_ports {GPI[0]}]
+set_property PACKAGE_PIN A8 [get_ports {GPI[0]}]
set_property PACKAGE_PIN C9 [get_ports {GPI[1]}]
set_property PACKAGE_PIN B9 [get_ports {GPI[2]}]
set_property PACKAGE_PIN B8 [get_ports {GPI[3]}]
@@ -55,12 +55,20 @@ set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 0.000 [g
##### reset #####
#************** reset is inverted
-set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.000 [get_ports reset]
-set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 2.000 [get_ports reset]
-set_max_delay -from [get_ports reset] 15.000
-set_false_path -from [get_ports reset]
-set_property PACKAGE_PIN C2 [get_ports {reset}]
-set_property IOSTANDARD LVCMOS33 [get_ports {reset}]
+set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.000 [get_ports resetn]
+set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 2.000 [get_ports resetn]
+set_max_delay -from [get_ports resetn] 15.000
+set_false_path -from [get_ports resetn]
+set_property PACKAGE_PIN C2 [get_ports {resetn}]
+set_property IOSTANDARD LVCMOS33 [get_ports {resetn}]
+
+
+set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.000 [get_ports south_reset]
+set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 2.000 [get_ports south_reset]
+set_max_delay -from [get_ports south_reset] 15.000
+set_false_path -from [get_ports south_reset]
+set_property PACKAGE_PIN D9 [get_ports {south_reset}]
+set_property IOSTANDARD LVCMOS33 [get_ports {south_reset}]
diff --git a/fpga/constraints/small-debug.xdc b/fpga/constraints/small-debug.xdc
index 4d943b5fc..3feeb03f4 100644
--- a/fpga/constraints/small-debug.xdc
+++ b/fpga/constraints/small-debug.xdc
@@ -82,13 +82,7 @@ connect_debug_port u_ila_0/probe11 [get_nets [list mb_reset ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe12]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
-connect_debug_port u_ila_0/probe12 [get_nets [list resetn ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe13]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
-connect_debug_port u_ila_0/probe13 [get_nets [list c0_ddr4_ui_clk_sync_rst ]]
-
+connect_debug_port u_ila_0/probe12 [get_nets [list c0_ddr4_ui_clk_sync_rst ]]
# the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock.
#connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk]
diff --git a/fpga/src/fpgaTopArtyA7.v b/fpga/src/fpgaTopArtyA7.v
index 915d58278..352d07ccf 100644
--- a/fpga/src/fpgaTopArtyA7.v
+++ b/fpga/src/fpgaTopArtyA7.v
@@ -29,6 +29,7 @@
module fpgaTop
(input default_100mhz_clk,
(* mark_debug = "true" *) input resetn,
+ input south_reset,
input [3:0] GPI,
output [4:0] GPO,
@@ -214,7 +215,7 @@ module fpgaTop
xlnx_proc_sys_reset xlnx_proc_sys_reset_0
(.slowest_sync_clk(CPUCLK),
.ext_reset_in(c0_ddr4_ui_clk_sync_rst),
- .aux_reset_in(1'b0),
+ .aux_reset_in(south_reset),
.mb_debug_sys_rst(1'b0),
.dcm_locked(c0_init_calib_complete),
.mb_reset(mb_reset), //open
@@ -353,7 +354,7 @@ module fpgaTop
.s_axi_rready(m_axi_rready),
.m_axi_aclk(BUSCLK),
- .m_axi_aresetn(resetn),
+ .m_axi_aresetn(~resetn),
.m_axi_awid(BUS_axi_awid),
.m_axi_awlen(BUS_axi_awlen),
.m_axi_awsize(BUS_axi_awsize),
@@ -421,8 +422,8 @@ module fpgaTop
.ui_clk(BUSCLK),
.ui_clk_sync_rst(ui_clk_sync_rst),
- .aresetn(resetn),
- .sys_rst(~resetn),
+ .aresetn(~resetn),
+ .sys_rst(resetn),
.mmcm_locked(mmcm_locked),
// *** What are these?