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various formatting fixes and comments

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This commit is contained in:
Cedar Turek 2022-12-30 18:41:40 -08:00
parent 286e43807a
commit fb9a0c797f
12 changed files with 30 additions and 30 deletions
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2
pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv
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@ -69,8 +69,8 @@ module fdivsqrtexpcalc(
end
assign SXExp = {2'b0, Xe} - {{(`NE+1-`DIVBLEN){1'b0}}, ell} - (`NE+2)'(`BIAS);
assign SExp = {SXExp[`NE+1], SXExp[`NE+1:1]} + {2'b0, Bias};
// correct exponent for denormalized input's normalization shifts
assign DExp = ({2'b0, Xe} - {{(`NE+1-`DIVBLEN){1'b0}}, ell} - {2'b0, Ye} + {{(`NE+1-`DIVBLEN){1'b0}}, m} + {3'b0, Bias}) & {`NE+2{~XZero}};
assign Qe = Sqrt ? SExp : DExp;
endmodule

1
pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv
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@ -45,7 +45,6 @@ module fdivsqrtfgen4 (
assign FN2 = (UM << 2) | ((C << 2) & ~(C << 4));
// Choose which adder input will be used
always_comb
if (udigit[3]) F = F2;
else if (udigit[2]) F = F1;

6
pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
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@ -68,6 +68,9 @@ module fdivsqrtpreproc (
// Extract inputs, signs, zero, depending on W64 mode if applicable
assign signedDiv = ~Funct3E[0];
assign NegQuotE = AsE ^ BsE; // Quotient is negative
// Source handling
if (`XLEN==64) begin // 64-bit, supports W64
mux2 #(1) azeromux(~(|ForwardedSrcAE), ~(|ForwardedSrcAE[31:0]), W64E, AZeroE);
mux2 #(1) bzeromux(~(|ForwardedSrcBE), ~(|ForwardedSrcBE[31:0]), W64E, BZeroE);
@ -86,9 +89,6 @@ module fdivsqrtpreproc (
assign BZeroE = ~(|ForwardedSrcBE);
end
// Quotient is negative
assign NegQuotE = AsE ^ BsE;
// Force integer inputs to be postiive
mux2 #(`XLEN) posamux(AE, -AE, AsE, PosA);
mux2 #(`XLEN) posbmux(BE, -BE, BsE, PosB);

7
pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv
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@ -1,7 +1,7 @@
///////////////////////////////////////////
// fdivsqrtstage2.sv
//
// Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek
// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
// Modified:13 January 2022
//
// Purpose: Combined Divide and Square Root Floating Point and Integer Unit stage
@ -67,12 +67,13 @@ module fdivsqrtstage2 (
// Divisor multiple
always_comb
if (up) Dsel = DBar;
else if (uz) Dsel = '0; // qz
else if (uz) Dsel = '0;
else Dsel = {3'b000, 1'b1, D}; // un
// Partial Product Generation
// WSA, WCA = WS + WC - qD
assign AddIn = SqrtE ? F : Dsel;
mux2 #(`DIVb+4) addinmux(F, Dsel, SqrtE, AddIn);
//assign AddIn = SqrtE ? F : Dsel;
csa #(`DIVb+4) csa(WS, WC, AddIn, up&~SqrtE, WSA, WCA);
assign WSNext = WSA << 1;
assign WCNext = WCA << 1;

2
pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv
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@ -1,7 +1,7 @@
///////////////////////////////////////////
// fdivsqrtstage4.sv
//
// Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek
// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
// Modified:13 January 2022
//
// Purpose: Combined Divide and Square Root Floating Point and Integer Unit stage

2
pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv
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@ -43,7 +43,7 @@ module fdivsqrtuotfc2(
// bits to the quotient as they come.
logic [`DIVb:0] K;
assign K = (C[`DIVb:0] & ~(C[`DIVb:0] << 1));
assign K = (C[`DIVb:0] & ~(C[`DIVb:0] << 1)); // Thermometer to one hot encoding
always_comb begin
if (up) begin