various formatting fixes and comments

pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv

@@ -69,8 +69,8 @@ module fdivsqrtexpcalc(
   end
   assign SXExp = {2'b0, Xe} - {{(`NE+1-`DIVBLEN){1'b0}}, ell} - (`NE+2)'(`BIAS);
   assign SExp  = {SXExp[`NE+1], SXExp[`NE+1:1]} + {2'b0, Bias};
+  
   // correct exponent for denormalized input's normalization shifts
   assign DExp  = ({2'b0, Xe} - {{(`NE+1-`DIVBLEN){1'b0}}, ell} - {2'b0, Ye} + {{(`NE+1-`DIVBLEN){1'b0}}, m} + {3'b0, Bias}) & {`NE+2{~XZero}};
-  
   assign Qe = Sqrt ? SExp : DExp;
 endmodule

pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv

@@ -39,9 +39,9 @@ module fdivsqrtfgen2 (
   logic [`DIVb+3:0] FP, FN, FZ;
   logic [`DIVb+3:0] SExt, SMExt, CExt;
 
-  assign SExt = {3'b0, U};
+  assign SExt  = {3'b0, U};
   assign SMExt = {3'b0, UM};
-  assign CExt = {2'b11, C}; // extend C from Q2.k to Q4.k
+  assign CExt  = {2'b11, C}; // extend C from Q2.k to Q4.k
 
   // Generate for both positive and negative bits
   assign FP = ~(SExt << 1) & CExt;

pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv

@@ -42,14 +42,13 @@ module fdivsqrtfgen4 (
   assign F1  = ~(U << 1) & C;
   assign F0  = '0;
   assign FN1 = (UM << 1) | (C & ~(C << 3));
-  assign FN2 = (UM << 2) | ((C << 2)&~(C << 4));
+  assign FN2 = (UM << 2) | ((C << 2) & ~(C << 4));
 
   // Choose which adder input will be used
-
   always_comb
     if (udigit[3])       F = F2;
     else if (udigit[2])  F = F1;
     else if (udigit[1])  F = FN1;
     else if (udigit[0])  F = FN2;
-    else            F = F0;
+    else                 F = F0;
 endmodule

pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv

@@ -96,7 +96,7 @@ module fdivsqrtpostproc(
   // Determine if sticky bit is negative  // *** look for ways to optimize this.  Shift shouldn't be needed.
   assign Sum = WC + WS;
   assign NegStickyM = Sum[`DIVb+3];
-  mux2 #(`DIVb+1) preqmmux(FirstU, FirstUM, NegStickyM, PreQmM);// Select U or U-1 depending on negative sticky bit
+  mux2 #(`DIVb+1) preqmmux(FirstU, FirstUM, NegStickyM, PreQmM); // Select U or U-1 depending on negative sticky bit
   mux2 #(`DIVb+1)    qmmux(PreQmM, (PreQmM << 1), SqrtM, QmM);
 
   if (`IDIV_ON_FPU) begin // Int supported

pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv

@@ -68,6 +68,9 @@ module fdivsqrtpreproc (
 
     // Extract inputs, signs, zero, depending on W64 mode if applicable
     assign signedDiv = ~Funct3E[0];
+    assign NegQuotE = AsE ^ BsE; // Quotient is negative
+
+    // Source handling
     if (`XLEN==64) begin // 64-bit, supports W64
       mux2 #(1) azeromux(~(|ForwardedSrcAE), ~(|ForwardedSrcAE[31:0]), W64E, AZeroE);
       mux2 #(1) bzeromux(~(|ForwardedSrcBE), ~(|ForwardedSrcBE[31:0]), W64E, BZeroE);
@@ -86,9 +89,6 @@ module fdivsqrtpreproc (
       assign BZeroE = ~(|ForwardedSrcBE);
     end
 
-    // Quotient is negative
-    assign NegQuotE = AsE ^ BsE;
-    
     // Force integer inputs to be postiive
     mux2 #(`XLEN) posamux(AE, -AE, AsE, PosA);
     mux2 #(`XLEN) posbmux(BE, -BE, BsE, PosB);

pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv

@@ -56,6 +56,6 @@ module fdivsqrtqsel2 (
 
   // Produce digit = +1, 0, or -1
   assign up = magnitude & ~sign;
-  assign uz  = ~magnitude;
+  assign uz = ~magnitude;
   assign un = magnitude & sign;
 endmodule

pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv

@@ -31,10 +31,10 @@
 `include "wally-config.vh"
 
 module fdivsqrtqsel4 (
-  input logic [2:0] Dmsbs,
+  input  logic [2:0] Dmsbs,
-  input logic [4:0] Smsbs,
+  input  logic [4:0] Smsbs,
-  input logic [7:0] WSmsbs, WCmsbs,
+  input  logic [7:0] WSmsbs, WCmsbs,
-  input logic Sqrt, j1,
+  input  logic Sqrt, j1,
   output logic [3:0] udigit
 );
 	logic [6:0] Wmsbs;

pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv

@@ -31,10 +31,10 @@
 `include "wally-config.vh"
 
 module fdivsqrtqsel4cmp (
-  input logic [2:0] Dmsbs,
+  input  logic [2:0] Dmsbs,
-  input logic [4:0] Smsbs,
+  input  logic [4:0] Smsbs,
-  input logic [7:0] WSmsbs, WCmsbs,
+  input  logic [7:0] WSmsbs, WCmsbs,
-  input logic SqrtE, j1,
+  input  logic SqrtE, j1,
   output logic [3:0] udigit
 );
 	logic [6:0] Wmsbs;

pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // fdivsqrtstage2.sv
 //
-// Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek
+// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
 // Modified:13 January 2022
 //
 // Purpose: Combined Divide and Square Root Floating Point and Integer Unit stage
@@ -67,12 +67,13 @@ module fdivsqrtstage2 (
   // Divisor multiple
   always_comb
     if      (up) Dsel = DBar;
-    else if (uz) Dsel = '0; // qz
+    else if (uz) Dsel = '0;
     else         Dsel = {3'b000, 1'b1, D}; // un
 
   // Partial Product Generation
   //  WSA, WCA = WS + WC - qD
-  assign AddIn = SqrtE ? F : Dsel;
+  mux2 #(`DIVb+4) addinmux(F, Dsel, SqrtE, AddIn);
+  //assign AddIn = SqrtE ? F : Dsel;
   csa #(`DIVb+4) csa(WS, WC, AddIn, up&~SqrtE, WSA, WCA);
   assign WSNext = WSA << 1;
   assign WCNext = WCA << 1;

pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // fdivsqrtstage4.sv
 //
-// Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek
+// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
 // Modified:13 January 2022
 //
 // Purpose: Combined Divide and Square Root Floating Point and Integer Unit stage

pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv

@@ -43,7 +43,7 @@ module fdivsqrtuotfc2(
   //  bits to the quotient as they come.
   logic [`DIVb:0] K;
 
-  assign K = (C[`DIVb:0] & ~(C[`DIVb:0] << 1));
+  assign K = (C[`DIVb:0] & ~(C[`DIVb:0] << 1)); // Thermometer to one hot encoding
 
   always_comb begin
     if (up) begin

pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv

@@ -46,19 +46,19 @@ module fdivsqrtuotfc4(
   assign K3 = (C & ~(C << 2));      // 3K
 
   always_comb begin
-    if (udigit[3]) begin           // +2
+    if (udigit[3]) begin            // +2
       UNext  = U | K2;
       UMNext = U | K1;
-    end else if (udigit[2]) begin  // +1
+    end else if (udigit[2]) begin   // +1
       UNext  = U | K1;
       UMNext = U;
-    end else if (udigit[1]) begin  // -1
+    end else if (udigit[1]) begin   // -1
       UNext  = UM | K3;
       UMNext = UM | K2;
-    end else if (udigit[0]) begin  // -2
+    end else if (udigit[0]) begin   // -2
       UNext  = UM | K2;
       UMNext = UM | K1;
-    end else begin                    // 0
+    end else begin                  // 0
       UNext  = U;
       UMNext = UM | K3;
     end