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Fix misa bug

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This commit is contained in:
Domenico Ottolia 2021-04-22 00:59:07 -04:00
parent e336fbd108
commit fb8f244dab
1 changed files with 1 additions and 1 deletions
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wally-pipelined/src/privileged/csrm.sv
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@ -108,7 +108,7 @@ module csrm #(parameter
logic WritePMPADDRM [0:15]; logic WritePMPADDRM [0:15];
// MISA is hardwired. Spec says it could be written to disable features, but this is not supported by Wally // MISA is hardwired. Spec says it could be written to disable features, but this is not supported by Wally
assign MISA_REGW = {(`XLEN == 32 ? 2'b01 : 2'b10), {(`XLEN-28){1'b0}}, `MISA}; assign MISA_REGW = {(`XLEN == 32 ? 2'b01 : 2'b10), {(`XLEN-28){1'b0}}, {`MISA}[25:0]};
// Write machine Mode CSRs // Write machine Mode CSRs
assign WriteMSTATUSM = CSRMWriteM && (CSRAdrM == MSTATUS); assign WriteMSTATUSM = CSRMWriteM && (CSRAdrM == MSTATUS);