update sample program

tests/debug/simple/Makefile

@@ -1,15 +1,14 @@
 TARGET = simple
 
 $(TARGET).objdump: $(TARGET)
-	riscv64-unknown-elf-objdump -S -D $(TARGET) > $(TARGET).objdump
+	riscv64-unknown-elf-objdump -S -D $(TARGET).elf > $(TARGET).objdump
-	spike $(TARGET)
+
     
 $(TARGET): $(TARGET).c Makefile
-	riscv64-unknown-elf-gcc -o $(TARGET) -g\
+	riscv64-unknown-elf-gcc -o $(TARGET).elf -g\
 	  -march=rv64gc -mabi=lp64d -mcmodel=medany \
 	  -nostdlib -static -lm -fno-tree-loop-distribute-patterns \
-	  -T../../../examples/C/common/test.ld -I../../../examples/C/common/ \
+	  -Ttest.ld $(TARGET).c 
-	  $(TARGET).c ../../../examples/C/common/crt.S ../../../examples/C/common/syscalls.c
 
 clean:
-	rm -f $(TARGET) $(TARGET).objdump
+	rm -f $(TARGET).elf $(TARGET).objdump

tests/debug/simple/make.bak

@@ -0,0 +1,15 @@
+TARGET = simple
+
+$(TARGET).objdump: $(TARGET)
+	riscv64-unknown-elf-objdump -S -D $(TARGET) > $(TARGET).objdump
+	spike $(TARGET)
+    
+$(TARGET): $(TARGET).c Makefile
+	riscv64-unknown-elf-gcc -o $(TARGET) -g\
+	  -march=rv64gc -mabi=lp64d -mcmodel=medany \
+	  -nostdlib -static -lm -fno-tree-loop-distribute-patterns \
+	  -T../../../examples/C/common/test.ld -I../../../examples/C/common/ \
+	  $(TARGET).c ../../../examples/C/common/crt.S ../../../examples/C/common/syscalls.c
+
+clean:
+	rm -f $(TARGET) $(TARGET).objdump

tests/debug/simple/openocd.cfg

@@ -0,0 +1,38 @@
+# OpenOCD config file for Core V Wally
+# can find example material in /usr/share/openocd/scripts/
+
+adapter driver ftdi
+
+# when multiple adapters with the same vid_pid are connected (ex: arty-a7 and usb-jtag)
+# need to specify which usb port to drive
+# find numerical path using command "lsusb -t" (<bus>-<port>)
+adapter usb location 1-10.2
+
+ftdi vid_pid 0x0403 0x6010
+ftdi channel 0
+
+#TODO: figure out which of these bits need to be set
+# data MSB..LSB       direction (1:out) MSB..LSB
+# 0000'0000'0011'0000 0000'0000'0011'1011
+ftdi layout_init 0x0030 0x003b
+#ftdi layout_init 0x0008 0x001b
+
+transport select jtag
+adapter speed 1000
+#ftdi tdo_sample_edge falling
+
+set _CHIPNAME cvw
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1002A005
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-phys 0x8000000 -work-area-size 0x4000 -work-area-backup 0
+
+# enable memory access error reports
+riscv set_enable_virt2phys off
+riscv set_enable_virtual off
+
+init
+#jlink jtag 3
+halt
+

tests/debug/simple/simple.c

@@ -1,4 +1,3 @@
-#include <stdio.h>
 
 int main() {
 

tests/debug/simple/test.ld

@@ -0,0 +1,25 @@
+
+OUTPUT_ARCH( "riscv" )
+
+ENTRY(main)
+
+/*----------------------------------------------------------------------*/
+/* Sections                                                             */
+/*----------------------------------------------------------------------*/
+
+MEMORY {
+
+       ram(wxa!ri): ORIGIN = 0x80000000, LENGTH = 0x4000
+
+}
+
+SECTIONS {
+
+	 .text :
+	 {
+	 	 *(.text*)
+	 }
+	 > ram
+	   . = ALIGN(4);
+
+}