diff --git a/src/ieu/bmu/bitreverse.sv b/src/ieu/bmu/bitreverse.sv index 5d195d241..559bb0c09 100644 --- a/src/ieu/bmu/bitreverse.sv +++ b/src/ieu/bmu/bitreverse.sv @@ -4,9 +4,9 @@ // // Written: Kevin Kim and Kip Macsai-Goren // Created: 1 February 2023 -// Modified: +// Modified: 6 March 2023 // -// Purpose: Carry-Less multiplication top-level unit +// Purpose: Bit reverse submodule // // Documentation: RISC-V System on Chip Design Chapter *** // diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index d57aecfd7..3675a7114 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -3,9 +3,9 @@ // // Written: Kevin Kim // Created: 16 February 2023 -// Modified: +// Modified: 6 March 2023 // -// Purpose: Top level B instruction decoder +// Purpose: Top level bit manipulation instruction decoder // // Documentation: RISC-V System on Chip Design Chapter 4 (Section 4.1.4, Figure 4.8, Table 4.5) // diff --git a/src/ieu/bmu/byte.sv b/src/ieu/bmu/byte.sv index 2b98b83d6..19b71fc1e 100644 --- a/src/ieu/bmu/byte.sv +++ b/src/ieu/bmu/byte.sv @@ -1,11 +1,11 @@ /////////////////////////////////////////// -// clmul.sv +// byte.sv // // Written: Kevin Kim // Created: 1 February 2023 -// Modified: +// Modified: 6 March 2023 // -// Purpose: Carry-Less multiplication top-level unit +// Purpose: RISCV bitmanip byte-wise operation unit // // Documentation: RISC-V System on Chip Design Chapter *** // diff --git a/src/ieu/bmu/clmul.sv b/src/ieu/bmu/clmul.sv index 46893573c..16d600b43 100644 --- a/src/ieu/bmu/clmul.sv +++ b/src/ieu/bmu/clmul.sv @@ -1,11 +1,11 @@ /////////////////////////////////////////// -// clmul.sv (carry-less multiplier) +// clmul.sv // // Written: Kevin Kim and Kip Macsai-Goren // Created: 1 February 2023 // Modified: // -// Purpose: Carry-Less multiplication top-level unit +// Purpose: Carry-Less multiplication unit // // Documentation: RISC-V System on Chip Design Chapter *** // diff --git a/src/ieu/bmu/ext.sv b/src/ieu/bmu/ext.sv index 0b4103273..3a832de65 100644 --- a/src/ieu/bmu/ext.sv +++ b/src/ieu/bmu/ext.sv @@ -1,6 +1,6 @@ /////////////////////////////////////////// -// cnt.sv +// ext.sv // // Written: Kevin Kim // Created: 4 February 2023 diff --git a/src/ieu/bmu/popcnt.sv b/src/ieu/bmu/popcnt.sv index c82476a61..544c1344f 100644 --- a/src/ieu/bmu/popcnt.sv +++ b/src/ieu/bmu/popcnt.sv @@ -1,6 +1,6 @@ /////////////////////////////////////////// -// +// popccnt.sv // Written: Kevin Kim // Modified: 2/4/2023 // diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index f4b7eead8..54459db82 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -4,9 +4,9 @@ // // Written: Kevin Kim and Kip Macsai-Goren // Created: 2 February 2023 -// Modified: +// Modified: March 6 2023 // -// Purpose: RISC-V miscellaneous bit manipulation unit (subset of ZBB instructions) +// Purpose: RISC-V ZBB top level unit // // Documentation: RISC-V System on Chip Design Chapter *** // diff --git a/src/ieu/bmu/zbc.sv b/src/ieu/bmu/zbc.sv index fc4b17b76..c1ed706ba 100644 --- a/src/ieu/bmu/zbc.sv +++ b/src/ieu/bmu/zbc.sv @@ -3,9 +3,9 @@ // // Written: Kevin Kim and Kip Macsai-Goren // Created: 2 February 2023 -// Modified: +// Modified: 3 March 2023 // -// Purpose: RISC-V single bit manipulation unit (ZBC instructions) +// Purpose: RISC-V ZBC top-level unit // // Documentation: RISC-V System on Chip Design Chapter *** //